0.8 μ m 1.4 μ m基于柱型宏cell的CMOS SOG

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56716

Y. Okuno, M. Okabe, T. Arakawa, I. Tomioka, T. Ohno, T. Noda, Y. Kuramitsu

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引用次数: 2

摘要

柱状宏单元结构在实验电路布局中有利于提高硅的利用率。作为一种应用，已经开发了一个64-b倍频器，具有32kb RAM和65kb ROM，使用1.4 m晶体管栅极海(SOG)，采用0.8 μm双层金属CMOS。RAM的栅极密度为1.5 kg/mm2，位密度为1.9 kb/mm2, ROM为6.3/mm2

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0.8 μm 1.4 MTr. CMOS SOG based on column macro-cell

Column macro-cell architecture has been verified to be advantageous for increasing silicon utilization in experimental circuit layouts. As an application, a 64-b multiplier with 32-kb RAM and 65-kb ROM using a 1.4-M transistor sea of gates (SOG) has been developed, using 0.8-μm two-layer-metal CMOS. Gate density of 1.5 kg/mm2 and bit densities of 1.9 kb/mm2 for RAM and 6.3/mm2 for ROM have been achieved

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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