实现129 dB信噪比的三阶Sigma-Delta调制器数字抽取滤波器设计

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID) Pub Date : 2021-10-29 DOI:10.1109/asid52932.2021.9651718

Dongyu Li, Zhijie Chen, Xu Liu, Zhiqi Shen, Y. Xing, Peiyuan Wan

{"title":"实现129 dB信噪比的三阶Sigma-Delta调制器数字抽取滤波器设计","authors":"Dongyu Li, Zhijie Chen, Xu Liu, Zhiqi Shen, Y. Xing, Peiyuan Wan","doi":"10.1109/asid52932.2021.9651718","DOIUrl":null,"url":null,"abstract":"A digital decimation filter in a 3rd-order Sigma-Delta analog-to-digital converter (Σ-Δ ADC) is proposed in this paper. The digital filter consists of a cascaded integrator comb (CIC) filter, a compensation filter, a half-band filter, and a configurable decimation multiple module. CSD coding is used and the FIR filter structure is optimized in this paper to greatly reduce the area of the multiplier and the number of registers. The decimation factor can be configured from 512 to 4096, and the signal-to-noise ratio (SNR) performance increases with higher decimation factor. Cooperating with a 3rd-order 1-bit modulator, this design can achieve 129dB SNR with a 512 decimation factor. Simulation results shows that this design has realized the complete function of the digital sampling filter with configurable sampling multiples.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Digital Decimation Filter Design for a 3rd-Order Sigma-Delta Modulator with Achieving 129 dB SNR\",\"authors\":\"Dongyu Li, Zhijie Chen, Xu Liu, Zhiqi Shen, Y. Xing, Peiyuan Wan\",\"doi\":\"10.1109/asid52932.2021.9651718\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A digital decimation filter in a 3rd-order Sigma-Delta analog-to-digital converter (Σ-Δ ADC) is proposed in this paper. The digital filter consists of a cascaded integrator comb (CIC) filter, a compensation filter, a half-band filter, and a configurable decimation multiple module. CSD coding is used and the FIR filter structure is optimized in this paper to greatly reduce the area of the multiplier and the number of registers. The decimation factor can be configured from 512 to 4096, and the signal-to-noise ratio (SNR) performance increases with higher decimation factor. Cooperating with a 3rd-order 1-bit modulator, this design can achieve 129dB SNR with a 512 decimation factor. Simulation results shows that this design has realized the complete function of the digital sampling filter with configurable sampling multiples.\",\"PeriodicalId\":150884,\"journal\":{\"name\":\"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/asid52932.2021.9651718\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/asid52932.2021.9651718","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文提出了一种用于三阶Sigma-Delta模数转换器(Σ-Δ ADC)的数字抽取滤波器。该数字滤波器由级联积分器梳状(CIC)滤波器、补偿滤波器、半带滤波器和可配置抽取倍数模块组成。本文采用CSD编码，并对FIR滤波器结构进行了优化，大大减小了乘法器的面积和寄存器的数量。抽取系数可配置为512 ~ 4096，抽取系数越大，信噪比(SNR)性能越好。配合3阶1位调制器，本设计可实现129dB的信噪比，抽取系数为512。仿真结果表明，该设计实现了采样倍数可配置的数字采样滤波器的完整功能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Digital Decimation Filter Design for a 3rd-Order Sigma-Delta Modulator with Achieving 129 dB SNR

A digital decimation filter in a 3rd-order Sigma-Delta analog-to-digital converter (Σ-Δ ADC) is proposed in this paper. The digital filter consists of a cascaded integrator comb (CIC) filter, a compensation filter, a half-band filter, and a configurable decimation multiple module. CSD coding is used and the FIR filter structure is optimized in this paper to greatly reduce the area of the multiplier and the number of registers. The decimation factor can be configured from 512 to 4096, and the signal-to-noise ratio (SNR) performance increases with higher decimation factor. Cooperating with a 3rd-order 1-bit modulator, this design can achieve 129dB SNR with a 512 decimation factor. Simulation results shows that this design has realized the complete function of the digital sampling filter with configurable sampling multiples.

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来源期刊

2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)

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