基于反馈DAC的异步电平交叉ADC的设计与仿真

2017 International Conference on Signal Processing and Communication (ICSPC) Pub Date : 2017-07-01 DOI:10.1109/CSPC.2017.8305840

A. Antony, Shobha Rekh Paulson, D. Moni

{"title":"基于反馈DAC的异步电平交叉ADC的设计与仿真","authors":"A. Antony, Shobha Rekh Paulson, D. Moni","doi":"10.1109/CSPC.2017.8305840","DOIUrl":null,"url":null,"abstract":"Design and implementation of an asynchronous LC-ADC with feedback DAC in 180nm technology using cadence is presented in this paper. Operating at 110Hz using 0.8 V supply voltage, the ADC achieves 47dB SNDR for 684nW power consumption. This paper also presents a charge sharing 1 bit DAC with pseudo resistors and dummy devices suitable for an asynchronous level crossing ADC.","PeriodicalId":123773,"journal":{"name":"2017 International Conference on Signal Processing and Communication (ICSPC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design and simulation of asynchronous level crossing ADC using feedback DAC\",\"authors\":\"A. Antony, Shobha Rekh Paulson, D. Moni\",\"doi\":\"10.1109/CSPC.2017.8305840\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Design and implementation of an asynchronous LC-ADC with feedback DAC in 180nm technology using cadence is presented in this paper. Operating at 110Hz using 0.8 V supply voltage, the ADC achieves 47dB SNDR for 684nW power consumption. This paper also presents a charge sharing 1 bit DAC with pseudo resistors and dummy devices suitable for an asynchronous level crossing ADC.\",\"PeriodicalId\":123773,\"journal\":{\"name\":\"2017 International Conference on Signal Processing and Communication (ICSPC)\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International Conference on Signal Processing and Communication (ICSPC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSPC.2017.8305840\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Signal Processing and Communication (ICSPC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSPC.2017.8305840","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文介绍了一种采用cadence技术在180nm工艺下设计并实现的带反馈DAC的异步LC-ADC。该ADC工作频率为110Hz，电源电压为0.8 V，功耗为684nW, SNDR为47dB。本文还提出了一种具有伪电阻和虚拟器件的电荷共享1位DAC，适用于异步电平交叉ADC。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Design and simulation of asynchronous level crossing ADC using feedback DAC

Design and implementation of an asynchronous LC-ADC with feedback DAC in 180nm technology using cadence is presented in this paper. Operating at 110Hz using 0.8 V supply voltage, the ADC achieves 47dB SNDR for 684nW power consumption. This paper also presents a charge sharing 1 bit DAC with pseudo resistors and dummy devices suitable for an asynchronous level crossing ADC.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2017 International Conference on Signal Processing and Communication (ICSPC)

自引率

0.00%

发文量