Jingook Kim, Eunkyeong Park, Jongjoo Lee, K. Park, Youngwoo Park
{"title":"配电网同步开关输出缓冲器的新型目标阻抗","authors":"Jingook Kim, Eunkyeong Park, Jongjoo Lee, K. Park, Youngwoo Park","doi":"10.1109/EDAPS.2014.7030812","DOIUrl":null,"url":null,"abstract":"The output voltages at parallel simultaneous switching output (SSO) channels are affected by impedance of power distribution network (PDN) and SSO patterns. In this paper, a target impedance for PDN is directly extracted from the allowable signal output variations due to the SSO patterns.","PeriodicalId":387223,"journal":{"name":"2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Novel target impedance for power distribution network of simultaneous switching output (SSO) buffers\",\"authors\":\"Jingook Kim, Eunkyeong Park, Jongjoo Lee, K. Park, Youngwoo Park\",\"doi\":\"10.1109/EDAPS.2014.7030812\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The output voltages at parallel simultaneous switching output (SSO) channels are affected by impedance of power distribution network (PDN) and SSO patterns. In this paper, a target impedance for PDN is directly extracted from the allowable signal output variations due to the SSO patterns.\",\"PeriodicalId\":387223,\"journal\":{\"name\":\"2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAPS.2014.7030812\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAPS.2014.7030812","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel target impedance for power distribution network of simultaneous switching output (SSO) buffers
The output voltages at parallel simultaneous switching output (SSO) channels are affected by impedance of power distribution network (PDN) and SSO patterns. In this paper, a target impedance for PDN is directly extracted from the allowable signal output variations due to the SSO patterns.