Low-power high-speed signal processing: From iterative algorithm to analog circuits

Despite the progress made in digital signal processing during the last decades, the constraints imposed by high data rate wireless communications are becoming ever more stringent. The development of the wireless internet of things with a massive machine-to-machine communications raised the importance of power consumption for sophisticated algorithms, such as channel equalization or decoding. The strong link existing between computational speed and power consumption suggests an investigation of signal processing with energy efficiency as a prominent design choice. Therefore we revisit the topic of signal processing with analog circuits and its potential to increase the energy efficiency. Channel equalization is chosen as one application of nonlinear signal processing, and a vector equalizer based on a recur-rent neural network (RNN) structure is taken as an example to demonstrate the potential of state of the art in very large scale integration (VLSI) design. We show for this example that it is possible to achieve an energy requirement of few pJ/bit, an improvement of three to four orders of magnitude compared with the most energy efficient digital circuits. As a second example, we consider iterative decoding algorithm based on message passing. They can be represented by a generalized RNN structure. Again, this allows to derive an equivalent analog circuit. Compared to digital circuits, analog circuits allow to perform iterative decoding or equalization with increased computational speed, reduced chip area and power consumption.