{"title":"用于CHAMP的通用处理器元件封装","authors":"B. Box, J. Nieznanski","doi":"10.1109/NAECON.1995.521973","DOIUrl":null,"url":null,"abstract":"A generic approach for packaging advanced, application specific processors as well a future processing elements into a common JEDEC MCM (Multi-chip Module) footprint is presented and demonstrated. Usage of a common I/O scheme at the MCM level eases future device upgrades, maximizes module reuse and minimizes redesign. An 11-chip, Xilinx XC4025 FPGA (Field Programmable Gate Array) based MCM was designed and built as a compute element using our CHAMP (Configurable Hardware Algorithm Mappable Preprocessor) architecture as a prototype for demonstrating the validity of the common processor element packaging strategy. We have conservatively estimated that for a wide range of solutions, the CHAMP MCM offers a cumulative 100:1 improvement in size, weight, power, cycle time and cost compared to state-of-the-art, individually packaged DSPs and microprocessors on custom PCBs. The MCM design approach, implementation tradeoffs and experimental results for various measured performance parameters are also given.","PeriodicalId":171918,"journal":{"name":"Proceedings of the IEEE 1995 National Aerospace and Electronics Conference. NAECON 1995","volume":"99 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Common processor element packaging for CHAMP\",\"authors\":\"B. Box, J. Nieznanski\",\"doi\":\"10.1109/NAECON.1995.521973\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A generic approach for packaging advanced, application specific processors as well a future processing elements into a common JEDEC MCM (Multi-chip Module) footprint is presented and demonstrated. Usage of a common I/O scheme at the MCM level eases future device upgrades, maximizes module reuse and minimizes redesign. An 11-chip, Xilinx XC4025 FPGA (Field Programmable Gate Array) based MCM was designed and built as a compute element using our CHAMP (Configurable Hardware Algorithm Mappable Preprocessor) architecture as a prototype for demonstrating the validity of the common processor element packaging strategy. We have conservatively estimated that for a wide range of solutions, the CHAMP MCM offers a cumulative 100:1 improvement in size, weight, power, cycle time and cost compared to state-of-the-art, individually packaged DSPs and microprocessors on custom PCBs. The MCM design approach, implementation tradeoffs and experimental results for various measured performance parameters are also given.\",\"PeriodicalId\":171918,\"journal\":{\"name\":\"Proceedings of the IEEE 1995 National Aerospace and Electronics Conference. NAECON 1995\",\"volume\":\"99 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 1995 National Aerospace and Electronics Conference. NAECON 1995\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NAECON.1995.521973\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 1995 National Aerospace and Electronics Conference. NAECON 1995","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON.1995.521973","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A generic approach for packaging advanced, application specific processors as well a future processing elements into a common JEDEC MCM (Multi-chip Module) footprint is presented and demonstrated. Usage of a common I/O scheme at the MCM level eases future device upgrades, maximizes module reuse and minimizes redesign. An 11-chip, Xilinx XC4025 FPGA (Field Programmable Gate Array) based MCM was designed and built as a compute element using our CHAMP (Configurable Hardware Algorithm Mappable Preprocessor) architecture as a prototype for demonstrating the validity of the common processor element packaging strategy. We have conservatively estimated that for a wide range of solutions, the CHAMP MCM offers a cumulative 100:1 improvement in size, weight, power, cycle time and cost compared to state-of-the-art, individually packaged DSPs and microprocessors on custom PCBs. The MCM design approach, implementation tradeoffs and experimental results for various measured performance parameters are also given.