一个10位高速CMOS CAS宏单元

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56703

A. W. Vogt, I. Dedic

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引用次数: 3

摘要

采用3 μm双金属单多晶硅CMOS工艺制备了10位50 m采样/s数模转换器。转换器的结构选择是为了最小化芯片梯度、错配和晶体管参数、电源轨道电压降和其他非理想效应的影响。密切关注转换器的动态行为，以减少输出小故障和码相关失真

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A 10-bit high speed CMOS CAS macrocell

A 10-bit 50 M-sample/s digital-to-analog converter has been fabricated in a 3-μm, double-metal, single-polysilicon CMOS process. The architecture of the converter was chosen to minimize the effects of chip gradients, mismatches and transistor parameters, voltage drops in supply tracks, and other nonideal effects. Close attention was paid to the dynamic behavior of the converter to reduce output glitches and code-dependent distortion

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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