K. Takeuchi, T. Yamamoto, A. Tanabe, T. Matsuki, T. Kunio, M. Fukuma, K. Nakajima, H. Aizaki, H. Miyamoto, E. Ikawa
{"title":"0.15 /spl mu/m CMOS，可靠性和性能高","authors":"K. Takeuchi, T. Yamamoto, A. Tanabe, T. Matsuki, T. Kunio, M. Fukuma, K. Nakajima, H. Aizaki, H. Miyamoto, E. Ikawa","doi":"10.1109/IEDM.1993.347259","DOIUrl":null,"url":null,"abstract":"0.15 /spl mu/m CMOSFETs with high reliability and performance have been realized. The acceptable power supply voltage V/sub cc/ was estimated to be 1.9 V. A reasonably short ring oscillator delay of 33 ps was obtained for the 1.9 V V/sub cc/, maintaining an 0.4 V threshold voltage. Anomalous surface state generation and V/sub TH/ shift for the pMOS were observed, though the degradation was less severe than the nMOS.<<ETX>>","PeriodicalId":346650,"journal":{"name":"Proceedings of IEEE International Electron Devices Meeting","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"0.15 /spl mu/m CMOS with high reliability and performance\",\"authors\":\"K. Takeuchi, T. Yamamoto, A. Tanabe, T. Matsuki, T. Kunio, M. Fukuma, K. Nakajima, H. Aizaki, H. Miyamoto, E. Ikawa\",\"doi\":\"10.1109/IEDM.1993.347259\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"0.15 /spl mu/m CMOSFETs with high reliability and performance have been realized. The acceptable power supply voltage V/sub cc/ was estimated to be 1.9 V. A reasonably short ring oscillator delay of 33 ps was obtained for the 1.9 V V/sub cc/, maintaining an 0.4 V threshold voltage. Anomalous surface state generation and V/sub TH/ shift for the pMOS were observed, though the degradation was less severe than the nMOS.<<ETX>>\",\"PeriodicalId\":346650,\"journal\":{\"name\":\"Proceedings of IEEE International Electron Devices Meeting\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1993.347259\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1993.347259","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
0.15 /spl mu/m CMOS with high reliability and performance
0.15 /spl mu/m CMOSFETs with high reliability and performance have been realized. The acceptable power supply voltage V/sub cc/ was estimated to be 1.9 V. A reasonably short ring oscillator delay of 33 ps was obtained for the 1.9 V V/sub cc/, maintaining an 0.4 V threshold voltage. Anomalous surface state generation and V/sub TH/ shift for the pMOS were observed, though the degradation was less severe than the nMOS.<>
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