{"title":"模拟电路与数字电路最佳加速试验区介电击穿随时间变化的比较研究","authors":"Kexin Yang, Taizhi Liu, Rui Zhang, L. Milor","doi":"10.1109/DCIS.2017.8311628","DOIUrl":null,"url":null,"abstract":"This paper investigates not only the traditional reliability concern, frontend-of-line dielectric breakdown (GTDDB), but also the newly emerging wearout mechanism, Middle-of-Line (MOL) time dependent dielectric breakdown (MTDDB). The optimal accelerated test conditions for these mechanisms are presented, which involves separate test conditions for each mechanism. To perform circuit-level accelerated life test, the optimal conditions vary for analog and digital circuits and need to be carefully considered before conducting the tests. Only tests in the optimal region are able to reflect the lifetime of the target wearout mechanism. Circuit designers will benefit due to the fact that different test conditions detect different wearout mechanisms. Therefore, the accelerated tests will provide information on the causes of failure, and circuit designers can use this information to redesign their circuits in a more robust and reliable way.","PeriodicalId":136788,"journal":{"name":"2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A comparison study of time-dependent dielectric breakdown for analog and digital circuit's optimal accelerated test regions\",\"authors\":\"Kexin Yang, Taizhi Liu, Rui Zhang, L. Milor\",\"doi\":\"10.1109/DCIS.2017.8311628\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper investigates not only the traditional reliability concern, frontend-of-line dielectric breakdown (GTDDB), but also the newly emerging wearout mechanism, Middle-of-Line (MOL) time dependent dielectric breakdown (MTDDB). The optimal accelerated test conditions for these mechanisms are presented, which involves separate test conditions for each mechanism. To perform circuit-level accelerated life test, the optimal conditions vary for analog and digital circuits and need to be carefully considered before conducting the tests. Only tests in the optimal region are able to reflect the lifetime of the target wearout mechanism. Circuit designers will benefit due to the fact that different test conditions detect different wearout mechanisms. Therefore, the accelerated tests will provide information on the causes of failure, and circuit designers can use this information to redesign their circuits in a more robust and reliable way.\",\"PeriodicalId\":136788,\"journal\":{\"name\":\"2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCIS.2017.8311628\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCIS.2017.8311628","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A comparison study of time-dependent dielectric breakdown for analog and digital circuit's optimal accelerated test regions
This paper investigates not only the traditional reliability concern, frontend-of-line dielectric breakdown (GTDDB), but also the newly emerging wearout mechanism, Middle-of-Line (MOL) time dependent dielectric breakdown (MTDDB). The optimal accelerated test conditions for these mechanisms are presented, which involves separate test conditions for each mechanism. To perform circuit-level accelerated life test, the optimal conditions vary for analog and digital circuits and need to be carefully considered before conducting the tests. Only tests in the optimal region are able to reflect the lifetime of the target wearout mechanism. Circuit designers will benefit due to the fact that different test conditions detect different wearout mechanisms. Therefore, the accelerated tests will provide information on the causes of failure, and circuit designers can use this information to redesign their circuits in a more robust and reliable way.