Dual threshold voltage adder for robust sub-Vt operation in 65nm technology

With the increased focus on power efficiency, there is a push towards lowering the supply voltage and operating the design in the sub-threshold regime. While this is good for lowering the active power, it makes certain circuits more susceptible to single-event effects due to poor Ioff/Ion ratio. The 28-T mirror adder is a key building block for many arithmetic and digital signal processing systems. Yet, the mirror full adder is vulnerable to failure in sub-threshold operation due to its long chain of transistors in series and xor-parallel configuration. By replacing the transistors in the vulnerable configuration with low-Vt transistors, we are able to strengthen the circuit for sub-threshold operation. In this paper, we look at the effect of a dual-Vt version of the basic mirror adder circuit in the 65nm technology node.