用于标准细胞表征的区域高效可重构阵列振荡器

B. P. Das, H. Onodera
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引用次数: 5

摘要

当今数百万的数字集成电路设计高度依赖于标准单元库的质量。在本研究中,提出了一种基于全数字可重构阵列的测试结构,使用门延迟测量单元的可重构阵列来测试标准单元库中所有类型逻辑门的质量(即功能和性能)。通过测量可重构环振荡器(RO)周期/频率,利用最小二乘法估计栅极延迟。由于最小二乘法平均了被测RO周期内的随机噪声,因此可以准确地估计被测栅极延迟。可重构阵列结构可以很容易地将故障标准单元与非故障标准单元隔离开来。该测试结构具有面积效率,在180 nm和65 nm技术节点上,与普通基于ro的延迟测量相比,面积分别节省1.6倍和2倍。使用此可重构数组结构测试标准单元的子集。在工业180nm工艺节点上制作了测试芯片,以研究该方法的可行性。对20个芯片的测量结果进行了报告,显示了模内和模间的变化量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Area-efficient reconfigurable-array-based oscillator for standard cell characterisation
Today's multi-million digital integrated circuit design highly depends on the quality of the standard cell library. In this study, an all-digital reconfigurable-array-based test structure is presented to test the quality (i.e. functionality and performance) of all types of logic gates in the standard cell library using the reconfigurable array of gate delay measurement cell. The gate delay is estimated using the least squares method with measured reconfigurable ring oscillator's (RO) period/frequency. As the least squares method averages out the random noise in the measured RO period, measured gate delay is estimated accurately. The reconfigurable-array structure can easily isolate a faulty standard cell from a non-faulty standard cell. The test structure is area efficient with a saving of 1.6× and 2× area compared with the normal RO-based delay measurement in 180 nm and 65 nm technology node, respectively. A subset of standard cells is tested using this reconfigurable-array structure. A test chip has been fabricated in an industrial 180 nm technology node to study the feasibility of the approach. The measured results from 20 chips are reported to show the amount of within-die and die-to-die variation.
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