基于SoC的哈希函数加速的软硬件架构

Ovidiu Panait, L. Dumitriu, I. Susnea
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引用次数: 2

摘要

本文提出了一种用于硬件设计快速原型的架构,旨在加速Xilinx ZYNQ SoC上的加密哈希函数。该设计包括硬件和软件组件,使用DMA和自定义的AXI4-Stream ip实现最大性能和易于集成。加速哈希函数的硬件模块和运行Linux的处理器之间的通信链接可以直接从用户空间访问,从而提供快速调试/基准测试功能。作为概念验证,开发了一个定制的,流水线和优化的比特币矿工模块,以证明该基础设施的可行性,并评估其性能。提出的解决方案在Arty Z7-20开发板上实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hardware and Software Architecture for Accelerating Hash Functions Based on SoC
This paper presents an architecture for fast prototyping of hardware designs aiming to accelerate cryptographic hash functions on Xilinx ZYNQ SoC. The design include both hardware and software components, using DMA and custom AXI4-Stream IPs for maximum performance and easy integration. The communication link between the hardware module that accelerates hash functions and the processor running Linux is accessible directly from the user-space, providing fast debugging/benchmarking capabilities. As a proof-of-concept, a custom, pipelined and optimized bitcoin miner module was developed in order to demonstrate the feasibility of this infrastructure, and to evaluate its performance. The proposed solution was implemented on an Arty Z7-20 development board.
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