一种高效的8位CMOS模数转换器结构

ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425) Pub Date : 2000-11-13 DOI:10.1109/SMELEC.2000.932459

P. Tan, S.B. Suparjo, R. Wagiran, R. Sidek

{"title":"一种高效的8位CMOS模数转换器结构","authors":"P. Tan, S.B. Suparjo, R. Wagiran, R. Sidek","doi":"10.1109/SMELEC.2000.932459","DOIUrl":null,"url":null,"abstract":"An 8-bit CMOS analog-to-digital converter (ADC) has been designed using a more efficient architecture. The simplified multistep 8-bit ADC requires two 4-bit full-flash cycles by using a modified 4-bit full-flash ADC with a voltage estimator. The speed of this new architecture is similar to conventional half-flash ADC but the die area consumption is much less due to reduced numbers of comparators and resistors.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An efficient architecture of 8-bit CMOS analog-to-digital converter\",\"authors\":\"P. Tan, S.B. Suparjo, R. Wagiran, R. Sidek\",\"doi\":\"10.1109/SMELEC.2000.932459\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 8-bit CMOS analog-to-digital converter (ADC) has been designed using a more efficient architecture. The simplified multistep 8-bit ADC requires two 4-bit full-flash cycles by using a modified 4-bit full-flash ADC with a voltage estimator. The speed of this new architecture is similar to conventional half-flash ADC but the die area consumption is much less due to reduced numbers of comparators and resistors.\",\"PeriodicalId\":359114,\"journal\":{\"name\":\"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-11-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMELEC.2000.932459\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.2000.932459","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

采用更高效的结构设计了一种8位CMOS模数转换器(ADC)。简化的多步8位ADC使用带有电压估计器的改进4位全闪存ADC，需要两个4位全闪存周期。这种新架构的速度与传统的半闪存ADC相似，但由于比较器和电阻的数量减少，芯片面积消耗要少得多。

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An efficient architecture of 8-bit CMOS analog-to-digital converter

An 8-bit CMOS analog-to-digital converter (ADC) has been designed using a more efficient architecture. The simplified multistep 8-bit ADC requires two 4-bit full-flash cycles by using a modified 4-bit full-flash ADC with a voltage estimator. The speed of this new architecture is similar to conventional half-flash ADC but the die area consumption is much less due to reduced numbers of comparators and resistors.

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ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)

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