{"title":"制造后测量驱动的氧化物击穿可靠性预测和管理","authors":"Cheng Zhuo, D. Blaauw, D. Sylvester","doi":"10.1145/1687399.1687482","DOIUrl":null,"url":null,"abstract":"Oxide breakdown has become an increasingly pressing reliability issue in modern VLSI design with ultra-thin oxides. The conventional guard-band methodology assumes uniformly thin oxide thickness and results in overly pessimistic reliability estimation that severely degrades the system performance. In this study we present the use of limited post-fabrication measurements of oxide thicknesses from on-chip sensors to aid in the chip-level oxide breakdown reliability prediction and quantify the trade-off between reliability margin and system performance. Given the post-fabrication measurements, chip oxide breakdown reliability can be formulated as a conditional distribution that allows us to achieve a significantly more accurate chip lifetime estimation. The estimation is then used to individually tune the supply voltage of each chip for performance maximization while maintaining or improving the reliability. Experimental results show that the proposed method can achieve performance improvement of 19% on average and 27% at maximum for a design with up to 50 million devices, using merely 25 measurements per chip, while analysis time is only 0.4 second. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circuits-design aids General Terms Performance, Algorithms","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Post-fabrication measurement-driven oxide breakdown reliability prediction and management\",\"authors\":\"Cheng Zhuo, D. Blaauw, D. Sylvester\",\"doi\":\"10.1145/1687399.1687482\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Oxide breakdown has become an increasingly pressing reliability issue in modern VLSI design with ultra-thin oxides. The conventional guard-band methodology assumes uniformly thin oxide thickness and results in overly pessimistic reliability estimation that severely degrades the system performance. In this study we present the use of limited post-fabrication measurements of oxide thicknesses from on-chip sensors to aid in the chip-level oxide breakdown reliability prediction and quantify the trade-off between reliability margin and system performance. Given the post-fabrication measurements, chip oxide breakdown reliability can be formulated as a conditional distribution that allows us to achieve a significantly more accurate chip lifetime estimation. The estimation is then used to individually tune the supply voltage of each chip for performance maximization while maintaining or improving the reliability. Experimental results show that the proposed method can achieve performance improvement of 19% on average and 27% at maximum for a design with up to 50 million devices, using merely 25 measurements per chip, while analysis time is only 0.4 second. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circuits-design aids General Terms Performance, Algorithms\",\"PeriodicalId\":256358,\"journal\":{\"name\":\"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers\",\"volume\":\"73 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1687399.1687482\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1687399.1687482","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Post-fabrication measurement-driven oxide breakdown reliability prediction and management
Oxide breakdown has become an increasingly pressing reliability issue in modern VLSI design with ultra-thin oxides. The conventional guard-band methodology assumes uniformly thin oxide thickness and results in overly pessimistic reliability estimation that severely degrades the system performance. In this study we present the use of limited post-fabrication measurements of oxide thicknesses from on-chip sensors to aid in the chip-level oxide breakdown reliability prediction and quantify the trade-off between reliability margin and system performance. Given the post-fabrication measurements, chip oxide breakdown reliability can be formulated as a conditional distribution that allows us to achieve a significantly more accurate chip lifetime estimation. The estimation is then used to individually tune the supply voltage of each chip for performance maximization while maintaining or improving the reliability. Experimental results show that the proposed method can achieve performance improvement of 19% on average and 27% at maximum for a design with up to 50 million devices, using merely 25 measurements per chip, while analysis time is only 0.4 second. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circuits-design aids General Terms Performance, Algorithms