制造后测量驱动的氧化物击穿可靠性预测和管理

Cheng Zhuo, D. Blaauw, D. Sylvester
{"title":"制造后测量驱动的氧化物击穿可靠性预测和管理","authors":"Cheng Zhuo, D. Blaauw, D. Sylvester","doi":"10.1145/1687399.1687482","DOIUrl":null,"url":null,"abstract":"Oxide breakdown has become an increasingly pressing reliability issue in modern VLSI design with ultra-thin oxides. The conventional guard-band methodology assumes uniformly thin oxide thickness and results in overly pessimistic reliability estimation that severely degrades the system performance. In this study we present the use of limited post-fabrication measurements of oxide thicknesses from on-chip sensors to aid in the chip-level oxide breakdown reliability prediction and quantify the trade-off between reliability margin and system performance. Given the post-fabrication measurements, chip oxide breakdown reliability can be formulated as a conditional distribution that allows us to achieve a significantly more accurate chip lifetime estimation. The estimation is then used to individually tune the supply voltage of each chip for performance maximization while maintaining or improving the reliability. Experimental results show that the proposed method can achieve performance improvement of 19% on average and 27% at maximum for a design with up to 50 million devices, using merely 25 measurements per chip, while analysis time is only 0.4 second. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circuits-design aids General Terms Performance, Algorithms","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Post-fabrication measurement-driven oxide breakdown reliability prediction and management\",\"authors\":\"Cheng Zhuo, D. Blaauw, D. Sylvester\",\"doi\":\"10.1145/1687399.1687482\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Oxide breakdown has become an increasingly pressing reliability issue in modern VLSI design with ultra-thin oxides. The conventional guard-band methodology assumes uniformly thin oxide thickness and results in overly pessimistic reliability estimation that severely degrades the system performance. In this study we present the use of limited post-fabrication measurements of oxide thicknesses from on-chip sensors to aid in the chip-level oxide breakdown reliability prediction and quantify the trade-off between reliability margin and system performance. Given the post-fabrication measurements, chip oxide breakdown reliability can be formulated as a conditional distribution that allows us to achieve a significantly more accurate chip lifetime estimation. The estimation is then used to individually tune the supply voltage of each chip for performance maximization while maintaining or improving the reliability. Experimental results show that the proposed method can achieve performance improvement of 19% on average and 27% at maximum for a design with up to 50 million devices, using merely 25 measurements per chip, while analysis time is only 0.4 second. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circuits-design aids General Terms Performance, Algorithms\",\"PeriodicalId\":256358,\"journal\":{\"name\":\"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers\",\"volume\":\"73 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1687399.1687482\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1687399.1687482","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

摘要

氧化物击穿已成为现代超薄氧化物VLSI设计中日益紧迫的可靠性问题。传统的保护带方法假设均匀的薄氧化物厚度,导致过于悲观的可靠性估计,严重降低了系统性能。在这项研究中,我们提出了使用芯片上传感器对氧化物厚度进行有限的制造后测量,以帮助芯片级氧化物击穿可靠性预测,并量化可靠性裕度和系统性能之间的权衡。考虑到制造后的测量,芯片氧化物击穿可靠性可以制定为条件分布,使我们能够实现更准确的芯片寿命估计。然后使用估计单独调整每个芯片的电源电压,以实现性能最大化,同时保持或提高可靠性。实验结果表明,对于多达5000万个器件的设计,该方法平均性能提高19%,最大性能提高27%,每个芯片仅使用25次测量,分析时间仅为0.4秒。B.7.2[硬件]:集成电路-设计辅助工具,通用术语,性能,算法
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Post-fabrication measurement-driven oxide breakdown reliability prediction and management
Oxide breakdown has become an increasingly pressing reliability issue in modern VLSI design with ultra-thin oxides. The conventional guard-band methodology assumes uniformly thin oxide thickness and results in overly pessimistic reliability estimation that severely degrades the system performance. In this study we present the use of limited post-fabrication measurements of oxide thicknesses from on-chip sensors to aid in the chip-level oxide breakdown reliability prediction and quantify the trade-off between reliability margin and system performance. Given the post-fabrication measurements, chip oxide breakdown reliability can be formulated as a conditional distribution that allows us to achieve a significantly more accurate chip lifetime estimation. The estimation is then used to individually tune the supply voltage of each chip for performance maximization while maintaining or improving the reliability. Experimental results show that the proposed method can achieve performance improvement of 19% on average and 27% at maximum for a design with up to 50 million devices, using merely 25 measurements per chip, while analysis time is only 0.4 second. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circuits-design aids General Terms Performance, Algorithms
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CiteScore
4.60
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