{"title":"窄线连接Cu / Low-k过孔的应力释放特性","authors":"H.Y. Lin, S. Lee, A. Oates","doi":"10.1109/RELPHY.2008.4558989","DOIUrl":null,"url":null,"abstract":"We show that the mechanism of stress voiding in Cu/low-k vias is independent of width in the range 0.07 - 0.42 squarem. The resistance change associated with voiding shows saturation with stress time, implying that stress voiding is not a fundamental concern for continued feature size scaling. Stress voiding at narrow w is very sensitive to interconnect processing, and can give unexpected, large resistance increases with annealing.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Characterization of stress-voiding of Cu / Low-k vias attached to narrow lines\",\"authors\":\"H.Y. Lin, S. Lee, A. Oates\",\"doi\":\"10.1109/RELPHY.2008.4558989\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We show that the mechanism of stress voiding in Cu/low-k vias is independent of width in the range 0.07 - 0.42 squarem. The resistance change associated with voiding shows saturation with stress time, implying that stress voiding is not a fundamental concern for continued feature size scaling. Stress voiding at narrow w is very sensitive to interconnect processing, and can give unexpected, large resistance increases with annealing.\",\"PeriodicalId\":187696,\"journal\":{\"name\":\"2008 IEEE International Reliability Physics Symposium\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE International Reliability Physics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RELPHY.2008.4558989\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.2008.4558989","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Characterization of stress-voiding of Cu / Low-k vias attached to narrow lines
We show that the mechanism of stress voiding in Cu/low-k vias is independent of width in the range 0.07 - 0.42 squarem. The resistance change associated with voiding shows saturation with stress time, implying that stress voiding is not a fundamental concern for continued feature size scaling. Stress voiding at narrow w is very sensitive to interconnect processing, and can give unexpected, large resistance increases with annealing.
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