通过Verilog-AMS驱动模拟混合信号验证

Sri Chandra
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引用次数: 0

摘要

当今soc和应用的复杂性推动了对更快、更准确的混合信号验证的需求。此外,混合信号设计中模拟内容的百分比正在迅速增加。这需要改变思维方式:模拟和数字模块不能再独立验证。由于这些原因,Accellera一直引领Verilog-AMS标准的发展,以实现包含数千个模拟/数字接口连接的系统的精确混合信号设计验证。本次演讲将讨论由Verilog-AMS技术委员会推动的最新语言增强,以使模拟和混合信号设计的系统级分析更加高效和准确。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Driving Analog Mixed Signal Verification through Verilog-AMS
The complexity of today's SoCs and applications are driving the need for faster and more accurate mixed signal verification. Additionally the percentage of analog content in mixed-signal designs is increasing rapidly. This requires a change in mindset: no longer can the analog and digital modules be verified independantly. For these reasons Accellera has been leading the development of the Verilog-AMS standard, to enable accurate mixed signal design verification of systems containing thousands of analog/digital interface connections. The presentation will discuss the recent language enhancements that have been driven by the Verilog-AMS technical committee, to make system level analysis of analog and mixed signal designs much more efficient and accurate.
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