{"title":"关于定制抽取过滤器的实现","authors":"L. Naviner, J. Naviner","doi":"10.1109/ICIT.2004.1490304","DOIUrl":null,"url":null,"abstract":"This paper deals with customized implementation of decimation processors. Important aspects of design law decisions are considered under hardware impact point of view. Several implementation approaches and respective evaluations in terms of time and basic operators requirements are given as well as a summary of the steps involved in an ad hoc implementation.","PeriodicalId":136064,"journal":{"name":"2004 IEEE International Conference on Industrial Technology, 2004. IEEE ICIT '04.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"On customized decimation filter implementation\",\"authors\":\"L. Naviner, J. Naviner\",\"doi\":\"10.1109/ICIT.2004.1490304\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper deals with customized implementation of decimation processors. Important aspects of design law decisions are considered under hardware impact point of view. Several implementation approaches and respective evaluations in terms of time and basic operators requirements are given as well as a summary of the steps involved in an ad hoc implementation.\",\"PeriodicalId\":136064,\"journal\":{\"name\":\"2004 IEEE International Conference on Industrial Technology, 2004. IEEE ICIT '04.\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Conference on Industrial Technology, 2004. IEEE ICIT '04.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIT.2004.1490304\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Conference on Industrial Technology, 2004. IEEE ICIT '04.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIT.2004.1490304","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper deals with customized implementation of decimation processors. Important aspects of design law decisions are considered under hardware impact point of view. Several implementation approaches and respective evaluations in terms of time and basic operators requirements are given as well as a summary of the steps involved in an ad hoc implementation.