{"title":"支持并行总线接口和总线管理的VLSI芯片","authors":"J. Zahn","doi":"10.1109/CMPEUR.1989.93450","DOIUrl":null,"url":null,"abstract":"Several parallel-backplane buses have been standardized in the last years, each having a different bus structure. A number of VLSI interface chips are now available, especially for the widespread VME bus, each representing different levels and types of functionality. The author presents an overview of their features.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"162 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"VLSI chips supporting parallel bus interfacing and bus management\",\"authors\":\"J. Zahn\",\"doi\":\"10.1109/CMPEUR.1989.93450\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Several parallel-backplane buses have been standardized in the last years, each having a different bus structure. A number of VLSI interface chips are now available, especially for the widespread VME bus, each representing different levels and types of functionality. The author presents an overview of their features.<<ETX>>\",\"PeriodicalId\":304457,\"journal\":{\"name\":\"Proceedings. VLSI and Computer Peripherals. COMPEURO 89\",\"volume\":\"162 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. VLSI and Computer Peripherals. COMPEURO 89\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CMPEUR.1989.93450\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPEUR.1989.93450","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
VLSI chips supporting parallel bus interfacing and bus management
Several parallel-backplane buses have been standardized in the last years, each having a different bus structure. A number of VLSI interface chips are now available, especially for the widespread VME bus, each representing different levels and types of functionality. The author presents an overview of their features.<>