CalmRISC32的可测试性策略和DFT方法

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 1900-01-01 DOI:10.1109/APASIC.2000.896966

Hong-Sik Kim, Il Seok Seo, Sungho Kang, G. Han

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摘要

本文介绍了CalmRISC32的测试策略和可测试性设计(DFT)方法。CalmRISC32是一个32位微控制单元，由一个32位IU核、一个FPU和一个Cache单元组成。嵌入式存储器阵列采用存储器自检(BIST)测试，逻辑块采用指令级功能测试方法测试。为了提高测试效率，开发了一种新的扫描链方法，使用一个称为TSU(测试扫描单元)的模块。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Testability strategy and DFT methodology of CalmRISC32

This paper describes the test strategy and the DFT (Design for Testability) methodology of CalmRISC32. CalmRISC32 is a 32 bit microcontrol unit, which consists of a 32 bit IU core, an FPU and a Cache Unit. The embedded memory arrays are tested by memory BIST (Built-in Self Test) and the logic blocks are tested by functional test methodology at the instruction level. To increase the test efficiency, a new scan chain methodology using a module called a TSU (Test Scan Unit) is developed.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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