{"title":"基于32nm SOI CMOS的20gbit /s rfdac直接调制w波段发射机","authors":"H. Al-Rubaye, Gabriel M. Rebeiz","doi":"10.1109/CSICS.2016.7751014","DOIUrl":null,"url":null,"abstract":"This paper presents a 94 GHz transmitter chipset in 32nm SOI CMOS. The transmitter employs two 2- bit high-speed RFDACs driven in quadrature, 20 dB gain LO drivers and 30 Gbps high-speed digital retimers and deserializers. The transmitter chip is capable of supporting BPSK/PAM4/QPSK modulation schemes, at a saturated output power Psat of +4 dBm. A maximum data rate of 20 Gbps was achieved when operating in QPSK mode, and 12 Gbps in BPSK and PAM4 modes. The chip occupies 1.4 × 0.8 mm2, and consumes 110 mW in BPSK/PAM4 modes and 220 mW in QPSK mode, resulting in a state-of-the-art 9 pJ/bit and 11 pJ/bit efficiency, respectively.","PeriodicalId":183218,"journal":{"name":"2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 20 Gbit/s RFDAC-Based Direct-Modulation W-Band Transmitter in 32nm SOI CMOS\",\"authors\":\"H. Al-Rubaye, Gabriel M. Rebeiz\",\"doi\":\"10.1109/CSICS.2016.7751014\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 94 GHz transmitter chipset in 32nm SOI CMOS. The transmitter employs two 2- bit high-speed RFDACs driven in quadrature, 20 dB gain LO drivers and 30 Gbps high-speed digital retimers and deserializers. The transmitter chip is capable of supporting BPSK/PAM4/QPSK modulation schemes, at a saturated output power Psat of +4 dBm. A maximum data rate of 20 Gbps was achieved when operating in QPSK mode, and 12 Gbps in BPSK and PAM4 modes. The chip occupies 1.4 × 0.8 mm2, and consumes 110 mW in BPSK/PAM4 modes and 220 mW in QPSK mode, resulting in a state-of-the-art 9 pJ/bit and 11 pJ/bit efficiency, respectively.\",\"PeriodicalId\":183218,\"journal\":{\"name\":\"2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2016.7751014\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2016.7751014","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 20 Gbit/s RFDAC-Based Direct-Modulation W-Band Transmitter in 32nm SOI CMOS
This paper presents a 94 GHz transmitter chipset in 32nm SOI CMOS. The transmitter employs two 2- bit high-speed RFDACs driven in quadrature, 20 dB gain LO drivers and 30 Gbps high-speed digital retimers and deserializers. The transmitter chip is capable of supporting BPSK/PAM4/QPSK modulation schemes, at a saturated output power Psat of +4 dBm. A maximum data rate of 20 Gbps was achieved when operating in QPSK mode, and 12 Gbps in BPSK and PAM4 modes. The chip occupies 1.4 × 0.8 mm2, and consumes 110 mW in BPSK/PAM4 modes and 220 mW in QPSK mode, resulting in a state-of-the-art 9 pJ/bit and 11 pJ/bit efficiency, respectively.
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