Two novel power-down circuits on the 1Mb CMOS SRAM

Scaled SRAMs suffer from large power dissipation because both the number of cells and the transistor drivability increase. In CMOS SRAMs the automatic power down (APD) scheme ([I]) is widely used on the read operation. In the APD scheme, word lines and sense amplifiers to which idling current is indispensable, are activaled dynamically by a timer pulse which is generated from address transition demtors (ATDs). and the operation power on rather low frequency is reduced. In order to salvage the slowest bits and to improve yield. however, the APD timer pulse should be 1.0 1.5 times as wide as the access time. Therefore the APD scheme cannot conribule the power reduction under the'minimum operation cycle. Besides, the scheme doesn't function on the write operation. This paper describes two novel power down circuits suitable for high density CMOS SRAMs. One is self-timed power down (SPD) scheme which employs self-timed mechanism for the data read-out completion. The other is automatic power down scheme on the write operation (APDW). The effectiveness of these new circuits is demonstrated on a 1M bit CMOS SRAM.