虚拟嵌入式块:fpga中嵌入式元件的评估方法

C. H. Ho, P. Leong, W. Luk, S. Wilton, S. López-Buedo
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引用次数: 64

摘要

嵌入式元件,如块乘法器,越来越多地用于先进的现场可编程门阵列(FPGA)器件,以提高速度,面积和功耗的效率。本文描述了一种评估此类嵌入要素对效率影响的方法。该方法涉及在FPGA中创建虚拟元件,称为虚拟嵌入式块(veb),以模拟嵌入式元件的大小,位置和延迟。FPGA和CAD供应商提供的标准设计流程可用于带有veb的设计的映射、放置、路由和重新定时。然后可以使用FPGA供应商的时序分析工具推断出最终设计的速度和资源利用率。我们举例说明了这种方法的应用,以评估涉及支持浮点计算的嵌入元素的各种方案
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs
Embedded elements, such as block multipliers, are increasingly used in advanced field programmable gate array (FPGA) devices to improve efficiency in speed, area and power consumption. A methodology is described for assessing the impact of such embedded elements on efficiency. The methodology involves creating dummy elements, called virtual embedded blocks (VEBs), in the FPGA to model the size, position and delay of the embedded elements. The standard design flow offered by FPGA and CAD vendors can be used for mapping, placement, routing and retiming of designs with VEBs. The speed and resource utilisation of the resulting designs can then be inferred using the FPGA vendor's timing analysis tools. We illustrate the application of this methodology to the evaluation of various schemes of involving embedded elements that support floating-point computations
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