An economic method for fabrication sub-quarter-/spl mu/m gate doped-channel FET's by photolithography

This paper reports a new sub-0.5-/spl mu/m gate-length FET processing technique by using conventional i-line optical lithography. The key methodology is to thermally re-flow the patterned photo-resist upon two-step spin-coated SOG. According to this new process, the deposited gate metal has its final length and thickness be separately determined by taped resist profile and SOG thickness. The implemented gate length is as short as 0.41 /spl mu/m. Then it was successfully applied to fabrication of a newly designed hetero-doped-channel field-effect transistor with digital-graded In/sub x/Ga/sub 1-x/As multi-layer forming a HEMT-like channel. This digital-graded In/sub x/Ga/sub l-x/As channel by changing x values from 0.1 to 0.2 has most electrons be closer to gate metal. The measured sheet carrier density and mobility are 4.3 /spl times/ 10/sup 12/ cm/sup -2/ and 3560 cm/sup 2/V/sup -1/s/sup -1/ while the peak carrier concentration is larger than 1 /spl times/ 10/sup 19/ cm/sup -3/. A fabricated 0.41 /spl times/ 100 /spl mu/m/sup 2/ HDCFET exhibits the maximum transconductance of 370 mS/mm with an output current lager than 535 mA/mm and ft (f max) of 26 (32) GHz.