采用相位平均耦合环振荡器的高时间分辨率时数转换器

Daiki Ogata, R. Kamiya, Yusuke Toyoshima, K. Ohhata
{"title":"采用相位平均耦合环振荡器的高时间分辨率时数转换器","authors":"Daiki Ogata, R. Kamiya, Yusuke Toyoshima, K. Ohhata","doi":"10.1109/APCCAS55924.2022.10090266","DOIUrl":null,"url":null,"abstract":"This paper proposes a high-time-resolution time to digital converter (TDC) using a coupled ring oscillator (CRO) with phase averaging. The CRO can generate short time interval multiphase clocks, and combining it with a counter enables a high-time-resolution TDC with a wide input range and relatively small circuitry. In addition, the application of phase averaging to the CRO reduces the timing error due to mismatch. A novel sampling technique is also proposed to eliminate the sampling error due to counter delay and glitches. Post-layout simulations were performed on a 10-bit TDC in 28-nm CMOS technology to evaluate the performance of the proposed TDC. The results showed that the high time resolution of 2.5 ps and low power dissipation of 15.6 m W at the sampling frequency of 350 MHz could be obtained, along with the FOM of 0.083 pJ/conv.-step.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"529 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A High-Time-Resolution Time-to-Digital Converter Using Coupled Ring Oscillator with Phase Averaging\",\"authors\":\"Daiki Ogata, R. Kamiya, Yusuke Toyoshima, K. Ohhata\",\"doi\":\"10.1109/APCCAS55924.2022.10090266\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a high-time-resolution time to digital converter (TDC) using a coupled ring oscillator (CRO) with phase averaging. The CRO can generate short time interval multiphase clocks, and combining it with a counter enables a high-time-resolution TDC with a wide input range and relatively small circuitry. In addition, the application of phase averaging to the CRO reduces the timing error due to mismatch. A novel sampling technique is also proposed to eliminate the sampling error due to counter delay and glitches. Post-layout simulations were performed on a 10-bit TDC in 28-nm CMOS technology to evaluate the performance of the proposed TDC. The results showed that the high time resolution of 2.5 ps and low power dissipation of 15.6 m W at the sampling frequency of 350 MHz could be obtained, along with the FOM of 0.083 pJ/conv.-step.\",\"PeriodicalId\":243739,\"journal\":{\"name\":\"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":\"529 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS55924.2022.10090266\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS55924.2022.10090266","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文提出了一种采用相位平均耦合环振荡器的高时间分辨率时数转换器(TDC)。CRO可以产生短时间间隔多相时钟,并与计数器相结合,使其具有宽输入范围和相对较小的电路的高时间分辨率TDC。此外,将相位平均应用于CRO,减小了由于失配引起的时序误差。提出了一种新的采样技术,以消除由于计数器延迟和小故障引起的采样误差。在28纳米CMOS技术的10位TDC上进行了布局后仿真,以评估所提出的TDC的性能。结果表明,在350 MHz的采样频率下,可获得2.5 ps的高时间分辨率和15.6 m W的低功耗,FOM为0.083 pJ/con .-step。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A High-Time-Resolution Time-to-Digital Converter Using Coupled Ring Oscillator with Phase Averaging
This paper proposes a high-time-resolution time to digital converter (TDC) using a coupled ring oscillator (CRO) with phase averaging. The CRO can generate short time interval multiphase clocks, and combining it with a counter enables a high-time-resolution TDC with a wide input range and relatively small circuitry. In addition, the application of phase averaging to the CRO reduces the timing error due to mismatch. A novel sampling technique is also proposed to eliminate the sampling error due to counter delay and glitches. Post-layout simulations were performed on a 10-bit TDC in 28-nm CMOS technology to evaluate the performance of the proposed TDC. The results showed that the high time resolution of 2.5 ps and low power dissipation of 15.6 m W at the sampling frequency of 350 MHz could be obtained, along with the FOM of 0.083 pJ/conv.-step.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信