Investigations of gate turn-off structures

R & D was carried out on gate turn-off devices, 1. An optimized, high speed epi-base GTO was developed. Fall times of <200ns and rise times 50A/cm2@ Tj=125°C. The fast trand tfresponse was obtained through a controlled gold distribution in the active device volume. A voltage source with series inductance at the gate will establish safe turn-off conditions; a 1.6KW switching capability @ 50kHz is calculated for a chip of 0.15cm2. 2. The introduction of anode shorts improves turn-off, however, turn-on sensitivity is substantially reduced. Replacing these shorts with Schottky barrier diodes fully restores the turn-on sensitivity. Devices with identical VT and similar turn-off capability, ≃ 30A @ 125°c, show about an order of magnitude improvement in turn-on sensitivity @ -40°C if Schottky barriers are added. 3. A dynamic ballasting concept was introduced. Through resistive, edge metalized cathodes the operational range for GTO's was extended from-60°C for turn-on (Igt=300µA) to +150°C for turn-off (J>55A/cm2) The formation of high current density filaments is countered.