The damage control of sub layer while ion-driven etching with vertical carbon profile implemented

As device scale down to sub 3nm, NMOS/PMOS boundary patterning becomes critical in logic product. This patterning requires highly directional etching while maintaining high selectivity to the base metal layer. In this paper, we demonstrated that the ion energy has the trade-off between the profile verticality and the surface damage. The ion energy was strongly controlled by the bias voltage and surface damage was improved with lower bias voltage, but profile verticality was deteriorated because of the ion angle dispersion. To enhance the profile verticality the carbon rich gas was added as the top passivation. The proposed method will be a practical in sub-3nm logic boundary patterning.