具有高SFDR的2.5 V 10 b 120 MSample/s CMOS流水线ADC

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012869

Sang-Min Yoo, Tae-Hwan Oh, J. Moon, Seunghoon Lee, U. Moon

{"title":"具有高SFDR的2.5 V 10 b 120 MSample/s CMOS流水线ADC","authors":"Sang-Min Yoo, Tae-Hwan Oh, J. Moon, Seunghoon Lee, U. Moon","doi":"10.1109/CICC.2002.1012869","DOIUrl":null,"url":null,"abstract":"A 10 b multibit-per-stage pipelined ADC incorporating the merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25 /spl mu/m CMOS process, occupies 3.6 mm/sup 2/ active die area and consumes 208 mW under a 2.5 V power supply.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"32","resultStr":"{\"title\":\"A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR\",\"authors\":\"Sang-Min Yoo, Tae-Hwan Oh, J. Moon, Seunghoon Lee, U. Moon\",\"doi\":\"10.1109/CICC.2002.1012869\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10 b multibit-per-stage pipelined ADC incorporating the merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25 /spl mu/m CMOS process, occupies 3.6 mm/sup 2/ active die area and consumes 208 mW under a 2.5 V power supply.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"32\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012869\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012869","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 32

摘要

采用合并电容开关(MCS)技术的10 b多比特/级流水线ADC在120 MSample/s下可实现53 dB SNDR，在输入频率高达奈奎斯特的100 MSample/s下可实现54 dB SNDR和68 dB SFDR。测得的DNL和INL分别为/spl plusmn/0.40 LSB和/spl plusmn/0.48 LSB。该ADC采用0.25 /spl μ m CMOS工艺制造，占用3.6 mm/sup / /有源芯片面积，在2.5 V电源下功耗为208 mW。

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A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR

A 10 b multibit-per-stage pipelined ADC incorporating the merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25 /spl mu/m CMOS process, occupies 3.6 mm/sup 2/ active die area and consumes 208 mW under a 2.5 V power supply.

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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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