On Optimized Manufacture of Bipolar Hetero transistors in a High-Voltage Element or for Increasing of their Integration Rate. Accounting Mismatch-Induced Stress

In the present time several actual problems of the solid state electronics (such as increasing of performance, reliability and density of elements of integrated circuits: diodes, field-effect and bipolar transistors) are intensively solving [1-6]. To increase the performance of these devices it is attracted an interest determination of materials with higher values of charge carriers mobility [7-10]. One way to decrease dimensions of elements of integrated circuits is manufacturing them in thin film heterostructures [3-5,11]. In this case it is possible to use inhomogeneity of heterostructure and necessary optimization of doping of electronic materials [12,13] and development of epitaxial technology to improve these materials (including analysis of mismatch induced stress) [14-16]. An alternative approaches to increase dimensions of integrated circuits are using of laser and microwave types of annealing [17-19].