{"title":"基于cfa的快速瞬态响应LDO调节器","authors":"A. Saberkari, H. Martínez, E. Alarcón","doi":"10.1109/ISCAS.2012.6271990","DOIUrl":null,"url":null,"abstract":"In this paper a fast transient response low-dropout regulator (LDO) based on a current feedback amplifier (CFA) is presented. The utilized CFA consists of an open-loop voltage follower with output local current-current feedback based on a level-shifted flipped voltage follower (LSFVF) to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the power pass transistor results in high PSRR. The circuit does not require any internal compensation capacitor and is stable for a wide range of output load currents 0-100 mA and a 1μF output capacitor. Post-layout simulation results for a 0.35μm CMOS process reveal that the maximum output voltage deviation of the proposed LDO for 0-100mA load transient with rise and fall times of 10 and 100ns is only 3mV, and the PSRR is smaller than -56dB over the entire load current range.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Fast transient response CFA-based LDO regulator\",\"authors\":\"A. Saberkari, H. Martínez, E. Alarcón\",\"doi\":\"10.1109/ISCAS.2012.6271990\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a fast transient response low-dropout regulator (LDO) based on a current feedback amplifier (CFA) is presented. The utilized CFA consists of an open-loop voltage follower with output local current-current feedback based on a level-shifted flipped voltage follower (LSFVF) to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the power pass transistor results in high PSRR. The circuit does not require any internal compensation capacitor and is stable for a wide range of output load currents 0-100 mA and a 1μF output capacitor. Post-layout simulation results for a 0.35μm CMOS process reveal that the maximum output voltage deviation of the proposed LDO for 0-100mA load transient with rise and fall times of 10 and 100ns is only 3mV, and the PSRR is smaller than -56dB over the entire load current range.\",\"PeriodicalId\":283372,\"journal\":{\"name\":\"2012 IEEE International Symposium on Circuits and Systems\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE International Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2012.6271990\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2012.6271990","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper a fast transient response low-dropout regulator (LDO) based on a current feedback amplifier (CFA) is presented. The utilized CFA consists of an open-loop voltage follower with output local current-current feedback based on a level-shifted flipped voltage follower (LSFVF) to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the power pass transistor results in high PSRR. The circuit does not require any internal compensation capacitor and is stable for a wide range of output load currents 0-100 mA and a 1μF output capacitor. Post-layout simulation results for a 0.35μm CMOS process reveal that the maximum output voltage deviation of the proposed LDO for 0-100mA load transient with rise and fall times of 10 and 100ns is only 3mV, and the PSRR is smaller than -56dB over the entire load current range.
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