高密度逻辑技术与减少堆叠双栅极mosfet

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI:10.1109/SOI.2005.1563544

M. Chiang, Keunwoo Kim, C. Chuang, C. Tretz

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引用次数: 0

摘要

我们提出了一种高密度DG逻辑电路技术，通过在高V/sub / T/对称DG器件中扩展门对门耦合，利用独特的V/sub / T/调制效应。该方案减少了堆叠晶体管的数量(因此面积/电容和待机/动态功率)，并提高了性能。使用混合模式二维数值模拟对性能改进和功耗降低进行了评估/验证。

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High-density logic techniques with reduced-stack double-gate MOSFETs

We have presented a high-density DG logic circuit technique exploiting the unique V/sub T/ modulation effect through the extended gate-to-gate coupling in high-V/sub T/ symmetrical DG devices. The scheme reduces the number of stacked transistors (hence area/capacitance and standby/dynamic power), and improves performance. The performance improvement and power reduction are evaluated/validated using mixed-mode two-dimensional numerical simulations.

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2005 IEEE International SOI Conference Proceedings

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