一种多晶硅接触插头技术的特点

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI:10.1109/VMIC.1989.78048

J. Klein, F. Pintchovski, W. Paulson, D. Fisher, M. Swenson, Y. See

{"title":"一种多晶硅接触插头技术的特点","authors":"J. Klein, F. Pintchovski, W. Paulson, D. Fisher, M. Swenson, Y. See","doi":"10.1109/VMIC.1989.78048","DOIUrl":null,"url":null,"abstract":"Summary form only given. Polysilicon plug technology takes advantage of the desirable properties of LPCVD polysilicon (i.e. conformal step coverage, smooth texture, good etchability) to planarize submicron contacts. In addition, sputtered and CVD barrier metal layers are utilized to ensure good ohmic contact and maintain a low-resistance plug. It is shown that the polysilicon plugs completely fill the contact holes and provide a nearly planar surface for the sputtered aluminum. In addition, the RIS+CVD TiN barrier is highly conformal for all observed contact sizes. The specific contact resistance to n/sup +/ and p/sup +/ doped silicon was found to be less than 5*100/sup -7/ Omega -cm/sup 2/. To titanium silicide, the contact resistance dropped to below 2*10/sup -8/ Omega -cm/sup 2/. The composite resistivity of the polysilicon plug plus CVD and RIS TiN barrier was less than 5*100/sup -4/ Omega -cm/sup 2/. Shallow junction, contact-intensive diode structures exhibited good breakdown voltages and leakage current below 5 nA/cm/sup 2/. These results demonstrate a reproducible contact plug technology suitable for advanced MLM CMOS circuits.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Characteristics of a poly-silicon contact plug technology\",\"authors\":\"J. Klein, F. Pintchovski, W. Paulson, D. Fisher, M. Swenson, Y. See\",\"doi\":\"10.1109/VMIC.1989.78048\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. Polysilicon plug technology takes advantage of the desirable properties of LPCVD polysilicon (i.e. conformal step coverage, smooth texture, good etchability) to planarize submicron contacts. In addition, sputtered and CVD barrier metal layers are utilized to ensure good ohmic contact and maintain a low-resistance plug. It is shown that the polysilicon plugs completely fill the contact holes and provide a nearly planar surface for the sputtered aluminum. In addition, the RIS+CVD TiN barrier is highly conformal for all observed contact sizes. The specific contact resistance to n/sup +/ and p/sup +/ doped silicon was found to be less than 5*100/sup -7/ Omega -cm/sup 2/. To titanium silicide, the contact resistance dropped to below 2*10/sup -8/ Omega -cm/sup 2/. The composite resistivity of the polysilicon plug plus CVD and RIS TiN barrier was less than 5*100/sup -4/ Omega -cm/sup 2/. Shallow junction, contact-intensive diode structures exhibited good breakdown voltages and leakage current below 5 nA/cm/sup 2/. These results demonstrate a reproducible contact plug technology suitable for advanced MLM CMOS circuits.<<ETX>>\",\"PeriodicalId\":302853,\"journal\":{\"name\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"volume\":\"85 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VMIC.1989.78048\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VMIC.1989.78048","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

只提供摘要形式。多晶硅plug技术利用了LPCVD多晶硅的理想特性(即共形台阶覆盖，光滑的纹理，良好的可蚀刻性)来平化亚微米触点。此外，利用溅射和CVD阻挡金属层来确保良好的欧姆接触并保持低电阻插头。结果表明，多晶硅塞完全填充了接触孔，并为溅射铝提供了接近平面的表面。此外，RIS+CVD TiN势垒对于所有观察到的接触尺寸都是高度适形的。n/sup +/和p/sup +/掺杂硅的比接触电阻小于5*100/sup -7/ Omega -cm/sup 2/。对硅化钛，接触电阻降至2*10/sup -8/ ω -cm/sup 2/以下。多晶硅塞加CVD和RIS TiN阻挡层的复合电阻率小于5*100/sup -4/ Omega -cm/sup 2/。浅结、接触密集的二极管结构具有良好的击穿电压和低于5 nA/cm/sup 2/的漏电流。这些结果证明了一种适用于先进MLM CMOS电路的可重复接触插头技术。

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Characteristics of a poly-silicon contact plug technology

Summary form only given. Polysilicon plug technology takes advantage of the desirable properties of LPCVD polysilicon (i.e. conformal step coverage, smooth texture, good etchability) to planarize submicron contacts. In addition, sputtered and CVD barrier metal layers are utilized to ensure good ohmic contact and maintain a low-resistance plug. It is shown that the polysilicon plugs completely fill the contact holes and provide a nearly planar surface for the sputtered aluminum. In addition, the RIS+CVD TiN barrier is highly conformal for all observed contact sizes. The specific contact resistance to n/sup +/ and p/sup +/ doped silicon was found to be less than 5*100/sup -7/ Omega -cm/sup 2/. To titanium silicide, the contact resistance dropped to below 2*10/sup -8/ Omega -cm/sup 2/. The composite resistivity of the polysilicon plug plus CVD and RIS TiN barrier was less than 5*100/sup -4/ Omega -cm/sup 2/. Shallow junction, contact-intensive diode structures exhibited good breakdown voltages and leakage current below 5 nA/cm/sup 2/. These results demonstrate a reproducible contact plug technology suitable for advanced MLM CMOS circuits.<>

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Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference

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