V. Sklyarov, I. Skliarova, J. Silva, A. Rjabov, A. Sudnitson
{"title":"可扩展处理平台在fpga电路实验中的应用","authors":"V. Sklyarov, I. Skliarova, J. Silva, A. Rjabov, A. Sudnitson","doi":"10.1109/MELCON.2014.6820579","DOIUrl":null,"url":null,"abstract":"Extensible processing platforms combine a high performance multi-core processor with a programmable logic on the same microchip. The paper describes how such platform has been used to provide support for experiments with competitive devices implemented in the programmable logic. The processor receives initial data from a host PC, copies the data to memory, which can also be accessed from the reconfigurable logic, activates the analyzed devices that execute operations over the data, and collects the results from the devices that finally are transmitted to the host PC. There are two main contributions in the paper that are 1) the developed technique of interaction of the processing system with the reconfigurable logic through a shared memory window; 2) a set of experiments illustrating the technique.","PeriodicalId":103316,"journal":{"name":"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Application of extensible processing platforms for experiments with FPGA-based circuits\",\"authors\":\"V. Sklyarov, I. Skliarova, J. Silva, A. Rjabov, A. Sudnitson\",\"doi\":\"10.1109/MELCON.2014.6820579\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Extensible processing platforms combine a high performance multi-core processor with a programmable logic on the same microchip. The paper describes how such platform has been used to provide support for experiments with competitive devices implemented in the programmable logic. The processor receives initial data from a host PC, copies the data to memory, which can also be accessed from the reconfigurable logic, activates the analyzed devices that execute operations over the data, and collects the results from the devices that finally are transmitted to the host PC. There are two main contributions in the paper that are 1) the developed technique of interaction of the processing system with the reconfigurable logic through a shared memory window; 2) a set of experiments illustrating the technique.\",\"PeriodicalId\":103316,\"journal\":{\"name\":\"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MELCON.2014.6820579\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MELCON.2014.6820579","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Application of extensible processing platforms for experiments with FPGA-based circuits
Extensible processing platforms combine a high performance multi-core processor with a programmable logic on the same microchip. The paper describes how such platform has been used to provide support for experiments with competitive devices implemented in the programmable logic. The processor receives initial data from a host PC, copies the data to memory, which can also be accessed from the reconfigurable logic, activates the analyzed devices that execute operations over the data, and collects the results from the devices that finally are transmitted to the host PC. There are two main contributions in the paper that are 1) the developed technique of interaction of the processing system with the reconfigurable logic through a shared memory window; 2) a set of experiments illustrating the technique.