可扩展处理平台在fpga电路实验中的应用

V. Sklyarov, I. Skliarova, J. Silva, A. Rjabov, A. Sudnitson
{"title":"可扩展处理平台在fpga电路实验中的应用","authors":"V. Sklyarov, I. Skliarova, J. Silva, A. Rjabov, A. Sudnitson","doi":"10.1109/MELCON.2014.6820579","DOIUrl":null,"url":null,"abstract":"Extensible processing platforms combine a high performance multi-core processor with a programmable logic on the same microchip. The paper describes how such platform has been used to provide support for experiments with competitive devices implemented in the programmable logic. The processor receives initial data from a host PC, copies the data to memory, which can also be accessed from the reconfigurable logic, activates the analyzed devices that execute operations over the data, and collects the results from the devices that finally are transmitted to the host PC. There are two main contributions in the paper that are 1) the developed technique of interaction of the processing system with the reconfigurable logic through a shared memory window; 2) a set of experiments illustrating the technique.","PeriodicalId":103316,"journal":{"name":"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Application of extensible processing platforms for experiments with FPGA-based circuits\",\"authors\":\"V. Sklyarov, I. Skliarova, J. Silva, A. Rjabov, A. Sudnitson\",\"doi\":\"10.1109/MELCON.2014.6820579\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Extensible processing platforms combine a high performance multi-core processor with a programmable logic on the same microchip. The paper describes how such platform has been used to provide support for experiments with competitive devices implemented in the programmable logic. The processor receives initial data from a host PC, copies the data to memory, which can also be accessed from the reconfigurable logic, activates the analyzed devices that execute operations over the data, and collects the results from the devices that finally are transmitted to the host PC. There are two main contributions in the paper that are 1) the developed technique of interaction of the processing system with the reconfigurable logic through a shared memory window; 2) a set of experiments illustrating the technique.\",\"PeriodicalId\":103316,\"journal\":{\"name\":\"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MELCON.2014.6820579\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"MELECON 2014 - 2014 17th IEEE Mediterranean Electrotechnical Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MELCON.2014.6820579","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

可扩展处理平台将高性能多核处理器与同一微芯片上的可编程逻辑相结合。本文描述了该平台如何为可编程逻辑实现的竞争器件的实验提供支持。处理器从主机PC接收初始数据,将数据复制到存储器(也可以从可重构逻辑访问存储器),激活对数据执行操作的被分析设备,并从最终传输到主机PC的设备收集结果。本文的主要贡献有两个:1)开发了通过共享内存窗口实现处理系统与可重构逻辑交互的技术;说明该技术的一组实验。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Application of extensible processing platforms for experiments with FPGA-based circuits
Extensible processing platforms combine a high performance multi-core processor with a programmable logic on the same microchip. The paper describes how such platform has been used to provide support for experiments with competitive devices implemented in the programmable logic. The processor receives initial data from a host PC, copies the data to memory, which can also be accessed from the reconfigurable logic, activates the analyzed devices that execute operations over the data, and collects the results from the devices that finally are transmitted to the host PC. There are two main contributions in the paper that are 1) the developed technique of interaction of the processing system with the reconfigurable logic through a shared memory window; 2) a set of experiments illustrating the technique.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信