带有片上电压限制器的实验性1Mb DRAM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156686

K. Itoh, R. Hori, Jun Etoh, S. Asai, N. Hashimoto, K. Yagi, H. Sunami

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引用次数: 63

摘要

本文将报道一个21μm2电池，单个5V 1Mb NMOS DRAM的实验。典型数据为:接入时间90ns，功耗300mW，周期时间260ns。芯片面积为46mm2

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An experimental 1Mb DRAM with on-chip voltage limiter

This paper will report on an experimental 21μm²cell, single 5V 1Mb NMOS DRAM. Typical clata are: access time 90ns, power dissipation 300mW at 260ns cycle time. Chip area is 46mm²

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1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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