{"title":"无电容分数阶滤波器和电容/电感模拟器","authors":"P. Bertsias, C. Psychalinos","doi":"10.1109/PACET.2017.8259965","DOIUrl":null,"url":null,"abstract":"Fractional-order filters as well as capacitor and inductor emulators, implemented using current-mirrors as active elements are presented in this work. Due to the utilization of the internal gate-source capacitance of MOS transistors or of the appropriately configured MOS transistors as capacitors, there is an absence of passive capacitors in the resulted structures. In addition, the small-signal transconductance parameter of the MOS transistors of current-mirrors is used for realizing the required resistors and, consequently, there is also an absence of passive resistors. The evaluation of the behavior of the proposed topologies has been performed using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35um CMOS process.","PeriodicalId":171095,"journal":{"name":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Capacitorless fractional-order filters and capacitor/inductor emulators\",\"authors\":\"P. Bertsias, C. Psychalinos\",\"doi\":\"10.1109/PACET.2017.8259965\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fractional-order filters as well as capacitor and inductor emulators, implemented using current-mirrors as active elements are presented in this work. Due to the utilization of the internal gate-source capacitance of MOS transistors or of the appropriately configured MOS transistors as capacitors, there is an absence of passive capacitors in the resulted structures. In addition, the small-signal transconductance parameter of the MOS transistors of current-mirrors is used for realizing the required resistors and, consequently, there is also an absence of passive resistors. The evaluation of the behavior of the proposed topologies has been performed using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35um CMOS process.\",\"PeriodicalId\":171095,\"journal\":{\"name\":\"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PACET.2017.8259965\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACET.2017.8259965","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Capacitorless fractional-order filters and capacitor/inductor emulators
Fractional-order filters as well as capacitor and inductor emulators, implemented using current-mirrors as active elements are presented in this work. Due to the utilization of the internal gate-source capacitance of MOS transistors or of the appropriately configured MOS transistors as capacitors, there is an absence of passive capacitors in the resulted structures. In addition, the small-signal transconductance parameter of the MOS transistors of current-mirrors is used for realizing the required resistors and, consequently, there is also an absence of passive resistors. The evaluation of the behavior of the proposed topologies has been performed using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35um CMOS process.