CMA:芯片多加速器

Dominik Auras, Sylvain Girbal, H. Berry, O. Temam, S. Yehia
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引用次数: 10

摘要

由于其提供的功率密度和性能效率,自定义加速已成为嵌入式系统中的标准选择。并行是另一种正交可伸缩性路径,它有效地克服了当前通用架构中频率缩放日益增加的限制。在本文中,我们提出了一种多加速器体系结构,它结合了并行性和自定义加速的优点,同时解决了异构多处理系统在可编程性方面的不便。芯片多加速器(CMA)是一种常规的并行架构,其中每个核心都有一个定制加速器来加速特定功能。此外,通过使用有效地将多个自定义加速器合并在一起的技术,我们能够根据应用程序或应用程序领域的需要填充尽可能多的加速器。我们在软件定义无线电(SDR)案例研究中演示了我们的方法。我们展示了从几种SDR波形和候选加速任务的基线描述开始,我们能够在异构多加速器架构上映射不同的波形,同时保持常规多核架构的逻辑视图,从而简化了波形到多加速器的映射。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
CMA: Chip multi-accelerator
Custom acceleration has been a standard choice in embedded systems thanks to the power density and performance efficiency it provides. Parallelism is another orthogonal scalability path that efficiently overcomes the increasing limitation of frequency scaling in current general-purpose architectures. In this paper we propose a multi-accelerator architecture that combines the best of both worlds, parallelism and custom acceleration, while addressing the programmability inconvenience of heterogeneous multiprocessing systems. A Chip Multi-Accelerator (CMA) is a regular parallel architecture where each core is complemented with a custom accelerator to speed up specific functions. Furthermore, by using techniques to efficiently merge more than one custom accelerator together, we are able to cram as many accelerators as needed by the application or a domain of applications. We demonstrate our approach on a Software Defined Radio (SDR) case study. We show that starting from a baseline description of several SDR waveforms and candidate tasks for acceleration, we are able to map the different waveforms on the heterogeneous multi-accelerator architecture while keeping a logical view of a regular multi-core architecture, thus simplifying the mapping of the waveforms onto the multi-accelerator.
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