{"title":"用于ULP应用的无掺杂DGFET的亚阈值模拟/射频性能估计","authors":"Anup Kumar, Chitrakant Sahu, Jawar Singh","doi":"10.1109/ICEMELEC.2014.7151211","DOIUrl":null,"url":null,"abstract":"In this paper, we report the potential of the doping-less (DL) double gate field effect transistor (DL-DGFET), for ultra low power (ULP) subthreshold logic applications. We demonstrated that the proposed DL-DGFET do not require any doping from source to drain region and it can perform significantly better than highly doped junctionless (JL) and abrupt S/D inversion-mode (IM) DGFETs. The DL-DGFET achieves 1.8X and 2.75X cutoff frequency (fT), 1.7X and 3X maximum frequency of oscillation (fMAX) along with 10.5 and 18.6 dB improvement in intrinsic voltage gain (AVO) in comparison to conventional JL and non-underlap FETs, respectively. Simulation results revealed that the DL-DGFET alleviates the inherent trade-off between gain and bandwidth of nanodevices by 6X improvement in gain frequency product (GFP) over highly doped JL-DGFET due to significant reduction in parasitic capacitances.","PeriodicalId":186054,"journal":{"name":"2014 IEEE 2nd International Conference on Emerging Electronics (ICEE)","volume":"21 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Subthreshold Analog/RF performance estimation of doping-less DGFET for ULP applications\",\"authors\":\"Anup Kumar, Chitrakant Sahu, Jawar Singh\",\"doi\":\"10.1109/ICEMELEC.2014.7151211\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we report the potential of the doping-less (DL) double gate field effect transistor (DL-DGFET), for ultra low power (ULP) subthreshold logic applications. We demonstrated that the proposed DL-DGFET do not require any doping from source to drain region and it can perform significantly better than highly doped junctionless (JL) and abrupt S/D inversion-mode (IM) DGFETs. The DL-DGFET achieves 1.8X and 2.75X cutoff frequency (fT), 1.7X and 3X maximum frequency of oscillation (fMAX) along with 10.5 and 18.6 dB improvement in intrinsic voltage gain (AVO) in comparison to conventional JL and non-underlap FETs, respectively. Simulation results revealed that the DL-DGFET alleviates the inherent trade-off between gain and bandwidth of nanodevices by 6X improvement in gain frequency product (GFP) over highly doped JL-DGFET due to significant reduction in parasitic capacitances.\",\"PeriodicalId\":186054,\"journal\":{\"name\":\"2014 IEEE 2nd International Conference on Emerging Electronics (ICEE)\",\"volume\":\"21 3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE 2nd International Conference on Emerging Electronics (ICEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEMELEC.2014.7151211\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE 2nd International Conference on Emerging Electronics (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEMELEC.2014.7151211","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Subthreshold Analog/RF performance estimation of doping-less DGFET for ULP applications
In this paper, we report the potential of the doping-less (DL) double gate field effect transistor (DL-DGFET), for ultra low power (ULP) subthreshold logic applications. We demonstrated that the proposed DL-DGFET do not require any doping from source to drain region and it can perform significantly better than highly doped junctionless (JL) and abrupt S/D inversion-mode (IM) DGFETs. The DL-DGFET achieves 1.8X and 2.75X cutoff frequency (fT), 1.7X and 3X maximum frequency of oscillation (fMAX) along with 10.5 and 18.6 dB improvement in intrinsic voltage gain (AVO) in comparison to conventional JL and non-underlap FETs, respectively. Simulation results revealed that the DL-DGFET alleviates the inherent trade-off between gain and bandwidth of nanodevices by 6X improvement in gain frequency product (GFP) over highly doped JL-DGFET due to significant reduction in parasitic capacitances.
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