{"title":"一种自底向上的VLSI电路中标准模块的放置和压缩方法","authors":"Dhiraj Sangwan, S. Verma, R. Kumar","doi":"10.1109/ICAES.2013.6659377","DOIUrl":null,"url":null,"abstract":"A bottom up approach for floor planning using the method of composite block formation using Macro Modules is presented. The process involves a recursive technique of bounding rectangle formation after searching the solution space using various number of composite block elements. The algorithm is efficient enough to reduce the dead space in range of 85-99 % and much quicker i.e. from 10 to 100 times faster as compared to standard iterative approaches to carryout floor planning in Electronic Design Automation tools.","PeriodicalId":114157,"journal":{"name":"2013 International Conference on Advanced Electronic Systems (ICAES)","volume":"36 10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A bottom up approach for placement and compaction of standard modules in VLSI circuit\",\"authors\":\"Dhiraj Sangwan, S. Verma, R. Kumar\",\"doi\":\"10.1109/ICAES.2013.6659377\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A bottom up approach for floor planning using the method of composite block formation using Macro Modules is presented. The process involves a recursive technique of bounding rectangle formation after searching the solution space using various number of composite block elements. The algorithm is efficient enough to reduce the dead space in range of 85-99 % and much quicker i.e. from 10 to 100 times faster as compared to standard iterative approaches to carryout floor planning in Electronic Design Automation tools.\",\"PeriodicalId\":114157,\"journal\":{\"name\":\"2013 International Conference on Advanced Electronic Systems (ICAES)\",\"volume\":\"36 10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 International Conference on Advanced Electronic Systems (ICAES)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAES.2013.6659377\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 International Conference on Advanced Electronic Systems (ICAES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAES.2013.6659377","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A bottom up approach for placement and compaction of standard modules in VLSI circuit
A bottom up approach for floor planning using the method of composite block formation using Macro Modules is presented. The process involves a recursive technique of bounding rectangle formation after searching the solution space using various number of composite block elements. The algorithm is efficient enough to reduce the dead space in range of 85-99 % and much quicker i.e. from 10 to 100 times faster as compared to standard iterative approaches to carryout floor planning in Electronic Design Automation tools.