A 32 x 9 ECL dual address register using an interleaving cell technique

A 32-WORD BY 9-BIT Dual Address Register Stack (DAS) which uses an interleaving ECL cell technique to achieve address access speeds comparable to previously-reported speeds for single port ECL memories' will be described. The ECL LSI device has two independent memory ports, each having full data, read/write capability, parity function and-output storage register. In addition, as shown in the functional block diagram, Figure 1, an error circuit signals when operations defined as system errors; e.g., simultaneous write to the same address, are performed. The parallel word, dual port, organization, requiring 18 input/output ports with individual data paths and a large amount of support error detection circuitry necessitated a compact storage cell to achieve a reasonable die size. At the same time ECL memory access speeds had to be maintained to fit the primary application as a register file in the "I0800 bit slize processor family. An ECL memory cell approach looked attractive in that high density and fast read/write performance could be achieved. However, because of the RAM voltage shift addressing mode and the small ECL cell voltage differential, the effect of cross port address and bit line changes on data integrity was feared. The dual cell approach adopted avoids these problems by essentially interleaving two independent memories, with an addressing activated write over capability. The interleaving technique provides the advantages of high port-to-port disturb isolation, a proven memory cell for the basic element and small cell size by utilization of integrated device techniques and minimization of isolation areas. Figure 2 illustrates the merged nature of an ECL memory cell, with load resistor, Schottky diode and two transistors in one isolation region. In the dual cell all emitter followers are placed in a common N region to further reduce array area.