Virtex II pro FPGA中坐标转换的低延迟实现

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI:10.1109/MIXDES.2007.4286132

G. Jablonski, K. Przygoda

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引用次数: 4

摘要

本文介绍了在Virtex II pro FPGA上实现笛卡尔-极坐标转换的低延迟实现。该模块的精度和资源消耗与Xilinx CORDIC IP Core相当，但延迟已减少到65%。本文还介绍了该转换模块在FLASH加速器低电平射频控制系统中腔体失谐计算中的应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Low-Latency Implementation of Coordinate Conversion in Virtex II pro FPGA

The paper presents a low-latency implementation of Cartesian-polar coordinate conversion in a Virtex II pro FPGA. The accuracy and resource consumption of the module is comparable to the one obtained with the Xilinx CORDIC IP Core, but the latency has been reduced to 65%. The application of the conversion module to the cavity detuning computation in low-level radio frequency control system for a FLASH accelerator has been also presented.

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2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

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