用于4gb / 16gb DRAM的正交6F/sup /沟槽侧壁垂直器件单元

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) Pub Date : 2000-12-10 DOI:10.1109/IEDM.2000.904327

C. Radens, S. Kudelka, L. Nesbit, R. Malik, T. Dyer, C. Dubuc, T. Joseph, M. Seitz, L. Clevenger, N. Arnold, J. Mandelman, R. Divakaruni, D. Casarotto, D. Lea, V. C. Jaiprakash, J. Sim, J. Faltermeier, K. Low, J. Strane, S. Halle, Q. Ye, S. Bukofsky, U. Gruening, T. Schloesser, G. Bronner

{"title":"用于4gb / 16gb DRAM的正交6F/sup /沟槽侧壁垂直器件单元","authors":"C. Radens, S. Kudelka, L. Nesbit, R. Malik, T. Dyer, C. Dubuc, T. Joseph, M. Seitz, L. Clevenger, N. Arnold, J. Mandelman, R. Divakaruni, D. Casarotto, D. Lea, V. C. Jaiprakash, J. Sim, J. Faltermeier, K. Low, J. Strane, S. Halle, Q. Ye, S. Bukofsky, U. Gruening, T. Schloesser, G. Bronner","doi":"10.1109/IEDM.2000.904327","DOIUrl":null,"url":null,"abstract":"This paper describes a novel 6F/sup 2/ trench-capacitor DRAM with a trench-sidewall vertical-channel array transistor. The cell features a line/space pattern for the active area, single-sided buried-strap node contact, vertical transistor channel formed along the upper region of the trench capacitor, a device active area bounded by the isolation trench and capacitor collar, and a single bit contact per cell.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM\",\"authors\":\"C. Radens, S. Kudelka, L. Nesbit, R. Malik, T. Dyer, C. Dubuc, T. Joseph, M. Seitz, L. Clevenger, N. Arnold, J. Mandelman, R. Divakaruni, D. Casarotto, D. Lea, V. C. Jaiprakash, J. Sim, J. Faltermeier, K. Low, J. Strane, S. Halle, Q. Ye, S. Bukofsky, U. Gruening, T. Schloesser, G. Bronner\",\"doi\":\"10.1109/IEDM.2000.904327\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a novel 6F/sup 2/ trench-capacitor DRAM with a trench-sidewall vertical-channel array transistor. The cell features a line/space pattern for the active area, single-sided buried-strap node contact, vertical transistor channel formed along the upper region of the trench capacitor, a device active area bounded by the isolation trench and capacitor collar, and a single bit contact per cell.\",\"PeriodicalId\":276800,\"journal\":{\"name\":\"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2000.904327\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2000.904327","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

本文介绍了一种采用沟槽边壁垂直通道阵列晶体管的新型6F/sup /沟槽电容DRAM。该单元具有用于有源区域的线/空间图案、单面埋带节点触点、沿沟槽电容器上部区域形成的垂直晶体管通道、由隔离沟槽和电容器环限定的器件有源区域以及每个单元的单位触点。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM

This paper describes a novel 6F/sup 2/ trench-capacitor DRAM with a trench-sidewall vertical-channel array transistor. The cell features a line/space pattern for the active area, single-sided buried-strap node contact, vertical transistor channel formed along the upper region of the trench capacitor, a device active area bounded by the isolation trench and capacitor collar, and a single bit contact per cell.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)

自引率

0.00%

发文量