一种用于ASIC的嵌入式动态逻辑电路触发器设计

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896898

K. Hirairi, H. Kosaka, K. Moriki, K. Keino, K. Onuma

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引用次数: 0

摘要

本文报道了一种采用标准单元设计的具有数据路径动态逻辑电路的触发器。触发器通过动态逻辑电路提供快速的逻辑运算，并通过抑制故障降低数据路径的总功耗。在基准测试中，采用绝对差分单元进行运动估计。通过使用触发器，该单元的速度比使用传统的d - ff快20%至40%，功耗降低20%至50%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A dynamic logic circuit embedded flip-flop for ASIC design

We report a flip-flop with a dynamic logic circuit for data path designed with standard cell. The flip-flop provides fast logic operation by the dynamic logic circuit and reduces total power dissipation of a data path by suppressing glitches. An absolute difference unit for motion estimation is used in a benchmark test. By using the flip-flop, the unit is 20% to 40% faster and has 20% to 50% less power dissipation than when conventional D-FFs are used.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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