低压CMOS电压平方器

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) Pub Date : 2009-12-01 DOI:10.1109/ICECS.2009.5410960

George Raikos, S. Vlassis

{"title":"低压CMOS电压平方器","authors":"George Raikos, S. Vlassis","doi":"10.1109/ICECS.2009.5410960","DOIUrl":null,"url":null,"abstract":"A voltage squarer based on bulk-driven PMOS transistors is proposed in this paper. Circuit topology employs a voltage attenuator and the quadratic ID/VG characteristic of a MOS in saturation. The squarer was designed with a 0.8V supply voltage using standard 0.35um CMOS process, which offers large value of threshold voltage. The squarer topology was modified for 0.18um CMOS process, which threshold voltage was smaller, operating under the extreme low supply voltage of 0.5V. The output current is proportional to square of the input voltage in each case. Simulation results verify the theoretical analysis demonstrating small relative error and fast transient response.","PeriodicalId":343974,"journal":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Low-voltage CMOS voltage squarer\",\"authors\":\"George Raikos, S. Vlassis\",\"doi\":\"10.1109/ICECS.2009.5410960\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A voltage squarer based on bulk-driven PMOS transistors is proposed in this paper. Circuit topology employs a voltage attenuator and the quadratic ID/VG characteristic of a MOS in saturation. The squarer was designed with a 0.8V supply voltage using standard 0.35um CMOS process, which offers large value of threshold voltage. The squarer topology was modified for 0.18um CMOS process, which threshold voltage was smaller, operating under the extreme low supply voltage of 0.5V. The output current is proportional to square of the input voltage in each case. Simulation results verify the theoretical analysis demonstrating small relative error and fast transient response.\",\"PeriodicalId\":343974,\"journal\":{\"name\":\"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2009.5410960\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2009.5410960","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

提出了一种基于体驱动PMOS晶体管的电压平方器。电路拓扑结构采用电压衰减器和MOS在饱和状态下的二次ID/VG特性。采用标准的0.35um CMOS工艺设计了0.8V电源电压，提供了较大的阈值电压。针对0.18um CMOS工艺改进了平方拓扑结构，使阈值电压更小，可在0.5V的极低电源电压下工作。在每种情况下，输出电流与输入电压的平方成正比。仿真结果验证了理论分析的正确性:相对误差小，瞬态响应快。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Low-voltage CMOS voltage squarer

A voltage squarer based on bulk-driven PMOS transistors is proposed in this paper. Circuit topology employs a voltage attenuator and the quadratic ID/VG characteristic of a MOS in saturation. The squarer was designed with a 0.8V supply voltage using standard 0.35um CMOS process, which offers large value of threshold voltage. The squarer topology was modified for 0.18um CMOS process, which threshold voltage was smaller, operating under the extreme low supply voltage of 0.5V. The output current is proportional to square of the input voltage in each case. Simulation results verify the theoretical analysis demonstrating small relative error and fast transient response.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

自引率

0.00%

发文量