{"title":"高密度层压板技术在Scm-L和Mcm-L中的应用策略","authors":"T. Houston, H. Heck, J. Knight","doi":"10.1109/ICMCM.1994.753546","DOIUrl":null,"url":null,"abstract":"As the electronics packaging industry turns toward MCM-L technology to provide higher performance, lower cost packaging solutions the demands on laminate technology increase. Increasing chip I/O places more challenging requirements on the laminate wiring density. The design considerations that drive circuit density are I/O escape and global interconnect. This paper discusses IBM Endicott's approach to addressing the escape requirements using a set of hi density laminate technologies. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"82 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Application Strategy for Scm-L and Mcm-L Using High Density Laminate Technologies\",\"authors\":\"T. Houston, H. Heck, J. Knight\",\"doi\":\"10.1109/ICMCM.1994.753546\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As the electronics packaging industry turns toward MCM-L technology to provide higher performance, lower cost packaging solutions the demands on laminate technology increase. Increasing chip I/O places more challenging requirements on the laminate wiring density. The design considerations that drive circuit density are I/O escape and global interconnect. This paper discusses IBM Endicott's approach to addressing the escape requirements using a set of hi density laminate technologies. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging.\",\"PeriodicalId\":363745,\"journal\":{\"name\":\"Proceedings of the International Conference on Multichip Modules\",\"volume\":\"82 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the International Conference on Multichip Modules\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMCM.1994.753546\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the International Conference on Multichip Modules","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMCM.1994.753546","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Application Strategy for Scm-L and Mcm-L Using High Density Laminate Technologies
As the electronics packaging industry turns toward MCM-L technology to provide higher performance, lower cost packaging solutions the demands on laminate technology increase. Increasing chip I/O places more challenging requirements on the laminate wiring density. The design considerations that drive circuit density are I/O escape and global interconnect. This paper discusses IBM Endicott's approach to addressing the escape requirements using a set of hi density laminate technologies. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging.