高密度层压板技术在Scm-L和Mcm-L中的应用策略

T. Houston, H. Heck, J. Knight
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引用次数: 0

摘要

随着电子封装行业转向MCM-L技术以提供更高性能,更低成本的封装解决方案,对层压板技术的需求增加。增加芯片I/O对层压板布线密度提出了更具挑战性的要求。驱动电路密度的设计考虑因素是I/O逃逸和全局互连。本文讨论了IBM Endicott使用一组高密度层压技术来解决逃逸需求的方法。IBM的层压板载波是为满足芯片I/O需求而设计的。特别令人感兴趣的是逃避多行倒装芯片I/O的能力。当I/O排列在阵列或外围阵列配置中时,需要访问多个布线层。进入内部层压板层的关键是能够提供具有小捕获面积的细间距通孔。本文讨论了IBM Microelectronics为给定的芯片I/O配置提供适当的层压板解决方案所采用的方法。具体的例子显示了芯片I/O密度如何影响层压技术的物理特性。必须仔细权衡的其他因素包括材料特性,加工要求,电气和热性能以及与下一级包装的连接。IBM的层压板载波是为满足芯片I/O需求而设计的。特别令人感兴趣的是逃避多行倒装芯片I/O的能力。当I/O排列在阵列或外围阵列配置中时,需要访问多个布线层。进入内部层压板层的关键是能够提供具有小捕获面积的细间距通孔。本文讨论了IBM Microelectronics为给定的芯片I/O配置提供适当的层压板解决方案所采用的方法。具体的例子显示了芯片I/O密度如何影响层压技术的物理特性。必须仔细权衡的其他因素包括材料特性,加工要求,电气和热性能以及与下一级包装的连接。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Application Strategy for Scm-L and Mcm-L Using High Density Laminate Technologies
As the electronics packaging industry turns toward MCM-L technology to provide higher performance, lower cost packaging solutions the demands on laminate technology increase. Increasing chip I/O places more challenging requirements on the laminate wiring density. The design considerations that drive circuit density are I/O escape and global interconnect. This paper discusses IBM Endicott's approach to addressing the escape requirements using a set of hi density laminate technologies. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging.
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