{"title":"LWIR fpga高动态范围数字化读出集成电路设计","authors":"Jun Qiao, Xiao Wang, Yaohong Zhao","doi":"10.1109/ASICON47005.2019.8983439","DOIUrl":null,"url":null,"abstract":"This paper presents an optimized design of digitalized readout integrated circuits (ROICs) to enlarge the dynamic range of long wave infrared (LWIR) focal plane arrays (FPAs) with frame rate guaranteed. The proposed design adopts two-step quantization structure. Each readout cell contains a 9-bit analog-to-digital converter (AD) to realize the coarse quantization within 30µm pitch. A pipeline AD with 7.9ENoB is designed at the column bus to complement the fine quantization. The combined 16-bit output-code comprises 9-bit in-pixel code and 7-bit AD quantization results. Simulation results show that the resolution is 16-bit and the full well capacity is 640Me- with 5ms integration time and 1V analog conversion range. The SNR is 86dB with 199fF integration capacitor and the uncorrected transmission linearity is 99.93%. The proposed design compromises the resolution, frame rate and power consumption. The design is promising in the third-generation ROIC applications.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design of High Dynamic Range and Digitalized Readout Integrated Circuit for LWIR FPAs\",\"authors\":\"Jun Qiao, Xiao Wang, Yaohong Zhao\",\"doi\":\"10.1109/ASICON47005.2019.8983439\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an optimized design of digitalized readout integrated circuits (ROICs) to enlarge the dynamic range of long wave infrared (LWIR) focal plane arrays (FPAs) with frame rate guaranteed. The proposed design adopts two-step quantization structure. Each readout cell contains a 9-bit analog-to-digital converter (AD) to realize the coarse quantization within 30µm pitch. A pipeline AD with 7.9ENoB is designed at the column bus to complement the fine quantization. The combined 16-bit output-code comprises 9-bit in-pixel code and 7-bit AD quantization results. Simulation results show that the resolution is 16-bit and the full well capacity is 640Me- with 5ms integration time and 1V analog conversion range. The SNR is 86dB with 199fF integration capacitor and the uncorrected transmission linearity is 99.93%. The proposed design compromises the resolution, frame rate and power consumption. The design is promising in the third-generation ROIC applications.\",\"PeriodicalId\":319342,\"journal\":{\"name\":\"2019 IEEE 13th International Conference on ASIC (ASICON)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 13th International Conference on ASIC (ASICON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON47005.2019.8983439\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 13th International Conference on ASIC (ASICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON47005.2019.8983439","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of High Dynamic Range and Digitalized Readout Integrated Circuit for LWIR FPAs
This paper presents an optimized design of digitalized readout integrated circuits (ROICs) to enlarge the dynamic range of long wave infrared (LWIR) focal plane arrays (FPAs) with frame rate guaranteed. The proposed design adopts two-step quantization structure. Each readout cell contains a 9-bit analog-to-digital converter (AD) to realize the coarse quantization within 30µm pitch. A pipeline AD with 7.9ENoB is designed at the column bus to complement the fine quantization. The combined 16-bit output-code comprises 9-bit in-pixel code and 7-bit AD quantization results. Simulation results show that the resolution is 16-bit and the full well capacity is 640Me- with 5ms integration time and 1V analog conversion range. The SNR is 86dB with 199fF integration capacitor and the uncorrected transmission linearity is 99.93%. The proposed design compromises the resolution, frame rate and power consumption. The design is promising in the third-generation ROIC applications.