通过层分配提高高速存储系统的功率和信号完整性

2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2019-10-01 DOI:10.1109/EPEPS47316.2019.193236

Pei-Yang Weng, Chi-Hsuan Cheng, Tzong-Lin Wu, C. Chen, James Chen, E. Kuo, Chun-Lin Liao, B. Mutnury

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引用次数: 1

摘要

在高速系统中，来自电源的大开关电流严重降低了系统的性能。本文揭示了一个与功率完整性相关的信号完整性问题。高速存储子系统使用眼图来评估开关电流对SI的影响。研究了几个测试用例，以阐明开关电流引起的功率电压变化对信号的敏感性。利用全波仿真和电路仿真验证了噪声抗扰性的假设。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Improvement of Power and Signal Integrity through Layer Assignment in High-Speed Memory Systems

In high-speed systems, large switching current drawn from power supply seriously degrades the system performance. This paper discloses a signal integrity (SI) issue related to power integrity (PI). A high-speed memory subsystem is used to evaluate the impact of switching current on SI using eye diagrams. Several test cases are studied to clarify the signal susceptibility from the voltage variation of power due to switching current. Full-wave and circuit simulations are used to validate the hypothesis of noise immunity.

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来源期刊

2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)

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