一种具有自适应死区控制的新型双模同步高效降压变换器

Y. Chung, S. Rai Mahendra, W. Liou, Chih-Yung Cheng
{"title":"一种具有自适应死区控制的新型双模同步高效降压变换器","authors":"Y. Chung, S. Rai Mahendra, W. Liou, Chih-Yung Cheng","doi":"10.1109/ICCCAS.2010.5581939","DOIUrl":null,"url":null,"abstract":"A novel Dual-Mode Modulation Zero Current Detection (ZCD) & Adaptive deadtime architecture has been proposed in this paper that can be used in a DC to DC step-down switching regulator. The converter operates in the pulse width modulation (PWM) mode for heavy load conditions and in the pulse frequency modulation (PFM) mode for light load conditions. In both these operating modes, the converter shows very high power conversion efficiency. This structure also has an adaptive deadtime range mechanism that changes the deadtime depending on the load current. This helps in reducing the power consumption considerably. The architecture also provides better heavy load current conversion efficiency as compared to the other works in the literature. Also, it can help in avoiding the malfunctioning of the ZCD mechanism that happens in the PFM mode for low currents. The most important contribution of this work is that it can achieve a high efficiency above 94% and shows an increasing trend in the efficiency even at heavy load conditions. Also the other major contribution of the proposed design is that it can in general be applied not only to a buck regulator but also to a boost regulator and a buck-boost regulator. A high conversion efficiency of 95.8% has been achieved in this work at a load current of 150 mA. And for the load current operation range of 50 mA to 420 mA, the conversion efficiency reaches above 94%. This design uses the TSMC 0.35-µm 2P4M 5V polycide CMOS process. The input operating voltage range for this process is from 3 to 5 V.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"32 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A novel Dual-Mode synchronous high efficiency buck converter with Adaptive deadtime control\",\"authors\":\"Y. Chung, S. Rai Mahendra, W. Liou, Chih-Yung Cheng\",\"doi\":\"10.1109/ICCCAS.2010.5581939\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel Dual-Mode Modulation Zero Current Detection (ZCD) & Adaptive deadtime architecture has been proposed in this paper that can be used in a DC to DC step-down switching regulator. The converter operates in the pulse width modulation (PWM) mode for heavy load conditions and in the pulse frequency modulation (PFM) mode for light load conditions. In both these operating modes, the converter shows very high power conversion efficiency. This structure also has an adaptive deadtime range mechanism that changes the deadtime depending on the load current. This helps in reducing the power consumption considerably. The architecture also provides better heavy load current conversion efficiency as compared to the other works in the literature. Also, it can help in avoiding the malfunctioning of the ZCD mechanism that happens in the PFM mode for low currents. The most important contribution of this work is that it can achieve a high efficiency above 94% and shows an increasing trend in the efficiency even at heavy load conditions. Also the other major contribution of the proposed design is that it can in general be applied not only to a buck regulator but also to a boost regulator and a buck-boost regulator. A high conversion efficiency of 95.8% has been achieved in this work at a load current of 150 mA. And for the load current operation range of 50 mA to 420 mA, the conversion efficiency reaches above 94%. This design uses the TSMC 0.35-µm 2P4M 5V polycide CMOS process. The input operating voltage range for this process is from 3 to 5 V.\",\"PeriodicalId\":199950,\"journal\":{\"name\":\"2010 International Conference on Communications, Circuits and Systems (ICCCAS)\",\"volume\":\"32 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-07-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Communications, Circuits and Systems (ICCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCCAS.2010.5581939\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCCAS.2010.5581939","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

提出了一种新的双模调制零电流检测(ZCD)和自适应死区结构,可用于直流降压开关稳压器。该转换器在重负载条件下以脉宽调制(PWM)模式工作,在轻负载条件下以脉冲频率调制(PFM)模式工作。在这两种工作模式下,变换器都显示出非常高的功率转换效率。该结构还具有自适应死区范围机制,可根据负载电流改变死区时间。这有助于大大降低功耗。与文献中的其他作品相比,该架构还提供了更好的大负载电流转换效率。此外,它可以帮助避免在低电流的PFM模式下发生的ZCD机制故障。这项工作最重要的贡献是它可以达到94%以上的高效率,并且即使在重载条件下效率也有增加的趋势。另外,所提出的设计的另一个主要贡献是,它通常不仅可以应用于降压稳压器,还可以应用于升压稳压器和降压稳压器。在负载电流为150 mA的情况下,实现了95.8%的高转换效率。在负载电流50ma ~ 420ma工作范围内,转换效率达到94%以上。本设计采用台积电0.35µm 2P4M 5V多晶硅CMOS工艺。该过程的输入工作电压范围为3至5v。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A novel Dual-Mode synchronous high efficiency buck converter with Adaptive deadtime control
A novel Dual-Mode Modulation Zero Current Detection (ZCD) & Adaptive deadtime architecture has been proposed in this paper that can be used in a DC to DC step-down switching regulator. The converter operates in the pulse width modulation (PWM) mode for heavy load conditions and in the pulse frequency modulation (PFM) mode for light load conditions. In both these operating modes, the converter shows very high power conversion efficiency. This structure also has an adaptive deadtime range mechanism that changes the deadtime depending on the load current. This helps in reducing the power consumption considerably. The architecture also provides better heavy load current conversion efficiency as compared to the other works in the literature. Also, it can help in avoiding the malfunctioning of the ZCD mechanism that happens in the PFM mode for low currents. The most important contribution of this work is that it can achieve a high efficiency above 94% and shows an increasing trend in the efficiency even at heavy load conditions. Also the other major contribution of the proposed design is that it can in general be applied not only to a buck regulator but also to a boost regulator and a buck-boost regulator. A high conversion efficiency of 95.8% has been achieved in this work at a load current of 150 mA. And for the load current operation range of 50 mA to 420 mA, the conversion efficiency reaches above 94%. This design uses the TSMC 0.35-µm 2P4M 5V polycide CMOS process. The input operating voltage range for this process is from 3 to 5 V.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信