Efficient simulation of thermo-mechanical stress in the on-chip metallization of power semiconductors

Large power semiconductors are complex structures, their metallization usually containing many thousands of contacts or vias. Because of this, detailed FEM simulations of the whole device are nowadays not possible because of excessive simulation time. This paper introduces a simulation approach which allows quick identification of critical regions with respect to lifetime by a simplified simulation. For this, the complex layers are replaced by a much simpler equivalent layer, allowing a simulation of the whole device even including its package. In a second step, precise simulations taking all details of the structure into account are carried out, but only for the critical regions of interest. Thus, this approach gives detailed results where required with consideration of the whole structure including packaging. Further, the simulation time requirements are very moderate.