Logic synthesis for programmable logic design

This paper presents a logic synthesis system for field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) based on either the Verilog HDL or VHDL. It describes aspects of synthesis and optimization specific to FPGAs and CPLDs, in contrast to CMOS gate-arrays. Particular attention is paid to architecture specific optimization, both on register transfer and logic level. The concept of the design methodology is proven by a real-world implementation of an actual design.<>