Vedic-Based Squaring Circuit Using Parallel Prefix Adders

This paper proposes a novel method using Vedic mathematics for calculating the square of binary numbers. An improved Vedic multiplier architecture is used in the binary squaring circuit. The circuit is further improved by using parallel prefix adder. Parallel prefix adder provides the best delay performance at the expense of area overhead. In this work, the parallel prefix adders like Kogge-Stone adder, Brent-Kung adder, Sklansky adder, Ladner-Fischer adder and Han-Carlson adder are used. The circuit is designed in Verilog HDL. The circuit synthesis has been performed in Xilinx ISE 14.7. Simulation has been performed for 4-bit and 8-bit designs. Performance comparison has been performed taking into consideration several parameters measured on different FPGA families. An improved speed performance is observed in this paper when compared with the previously reported circuits.