7F/sup 2/ cell和位线架构，具有倾斜阵列器件和4gb DRAM的无惩罚垂直BL扭曲

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI:10.1109/VLSIC.1999.797259

H. Hoenigschmid, A. Frey, J. DeBrosse, T. Kirihata, G. Mueller, G. Daniel, G. Frankowsky, K. Guay, D. Hanson, L. Hsu, B. Ji, D. Netis, S. Panaroni, C. Radens, A. Reith, D. Storaska, O. Weinfurtner, J. Alsmeier, W. Weber, M. Wordeman

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引用次数: 0

摘要

采用0.175 /spl mu/m CMOS技术，制备了7F/sup 2/ DRAM单元和相应的垂直折叠位线结构。这一概念的特点是先进的30/spl度/倾斜阵列设备布局和一个区域罚扭之间BL。该方案通过最大限度地增加扭转段的数量来最小化局部井噪声。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4 Gb DRAM's

A 7F/sup 2/ DRAM cell and corresponding vertically folded bitline architecture has been fabricated using a 0.175 /spl mu/m CMOS technology. This concept features an advanced 30/spl deg/ tilted array device layout and an area penalty free inter BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals.

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来源期刊

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

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